DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 8

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS26528 Octal T1/E1/J1 Transceiver
Table 9-5. BERT Register List ................................................................................................................................... 98
Table 9-6. Global Register Bit Map............................................................................................................................ 99
Table 9-7. Framer Register Bit Map ........................................................................................................................ 100
Table 9-8. LIU Register Bit Map .............................................................................................................................. 108
Table 9-9. BERT Register Bit Map .......................................................................................................................... 108
Table 9-10. Global Register Set .............................................................................................................................. 109
Table 9-11. Backplane Reference Clock Select ...................................................................................................... 113
Table 9-12. Master Clock Input Selection................................................................................................................ 114
Table 9-13. Device ID Codes in this Product Family ............................................................................................... 117
Table 9-14. LIU Register Set ................................................................................................................................... 218
Table 9-15. Transmit Load Impedance Selection.................................................................................................... 219
Table 9-16. Transmit Pulse Shape Selection .......................................................................................................... 219
Table 9-17. Receive Level Indication....................................................................................................................... 224
Table 9-18. Receive Impedance Selection.............................................................................................................. 225
Table 9-19. Receiver Sensitivity Selection with Monitor Mode Disabled................................................................. 226
Table 9-20. Receiver Sensitivity Selection with Monitor Mode Enabled ................................................................. 226
Table 9-21. BERT Register Set ............................................................................................................................... 227
Table 9-22. BERT Pattern Select ............................................................................................................................ 229
Table 9-23. BERT Error Insertion Rate ................................................................................................................... 230
Table 9-24. BERT Repetitive Pattern Length Select ............................................................................................... 230
Table 11-1. Recommended DC Operating Conditions ............................................................................................ 250
Table 11-2. Capacitance.......................................................................................................................................... 250
Table 11-3. Recommended DC Operating Conditions ............................................................................................ 250
Table 11-4. Thermal Characteristics........................................................................................................................ 251
Table 11-5. Transmitter Characteristics................................................................................................................... 251
Table 11-6. Receiver Characteristics....................................................................................................................... 251
Table 12-1. AC Characteristics—Microprocessor Bus Timing ................................................................................ 252
Table 12-2. Receiver AC Characteristics ................................................................................................................ 255
Table 12-3. Transmit AC Characteristics................................................................................................................. 258
Table 12-4. JTAG Interface Timing.......................................................................................................................... 261
Table 12-5. System Clock AC Charateristics .......................................................................................................... 262
Table 13-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 267
Table 13-2. ID Code Structure................................................................................................................................. 268
Table 13-3. Boundary Scan Control Bits ................................................................................................................. 268
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