EVAL-ADCMP581BCPZ Analog Devices Inc, EVAL-ADCMP581BCPZ Datasheet - Page 7

• Manufacturer Part Number: EVAL-ADCMP581BCPZ
• Description: BOARD EVALUATION ADCMP581BCP
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADCMP581BCPZ

• Main Purpose: Interface, Comparator
• Utilized Ic / Part: ADCMP581
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5, 16
6
7
8
9, 12
10
11
13
14
15
Heat Sink
Paddle
Figure 3. ADCMP580 Pin Configuration
V
V
V
V
TN
TP
N
P
1
2
3
4
ADCMP580
Mnemonic
V
V
V
V
V
LE
LE
V
GND/V
Q
Q
V
HYS
GND
N/C
(Not to Scale)
TP
P
N
TN
CCI
TT
EE
TOP VIEW
PIN 1
INDICATOR
CCO
12 GND
11 Q
10
9 GND
Description
Termination Resistor Return Pin for VP Input.
Noninverting Analog Input.
Inverting Analog Input.
Termination Resistor Return Pin for V
Positive Supply Voltage.
Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of
the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator being
placed into latch mode. LE must be driven in complement with LE.
Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the
input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the
comparator being placed into latch mode. LE must be driven in complement with LE.
Termination Return Pin for the LE/LE Input Pins.
For the ADCMP580 (CML output stage), this pin should be connected to the GND ground.
For the ADCMP581 (ECL output stage), this pin should be connected to the –2 V termination potential.
For the ADCMP582 (PECL output stage), this pin should be connected to the V
Digital Ground Pin/Positive Logic Power Supply Terminal.
For the ADCMP580/ADCMP581, this pin should be connected to the GND pin.
For the ADCMP582, this pin should be connected to the positive logic power V
Inverting Output. Q is logic low if the analog voltage at the noninverting input, V
voltage at the inverting input, V
(Pin 6 to Pin 7) for more information.
Noninverting Output. Q is logic high if the analog voltage at the noninverting input, V
analog voltage at the inverting input, V
descriptions (Pin 6 to Pin 7) for more information.
Negative Power Supply.
Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the V
suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 9 for proper sizing of the HYS
hysteresis control resistor.
Analog Ground.
The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left
floating for optimal electrical isolation between the package handle and the substrate of the die. It can also
be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal
at package corners is connected to the heat sink paddle.
Q
Figure 4. ADCMP581 Pin Configuration
V
V
V
V
TN
TP
N
P
1
2
3
4
N
, provided that the comparator is in compare mode. See the LE/LE descriptions
Rev. A | Page 7 of 16
ADCMP581
(Not to Scale)
TOP VIEW
N
PIN 1
INDICATOR
Input.
N
, provided that the comparator is in compare mode. See the LE/LE
12 GND
11 Q
10
9 GND
Q
ADCMP580/ADCMP581/ADCMP582
Figure 5. ADCMP582 Pin Configuration
V
V
V
V
TP
TN
CCO
P
N
CCO
1
2
3
4
P
– 2 V termination potential.
, is greater than the analog
supply.
ADCMP582
(Not to Scale)
TOP VIEW
P
, is greater than the
PIN 1
INDICATOR
EE
supply with a
12 V
11 Q
10
9 V
Q
CCO
CCO