LTM4600HVIV#PBF Linear Technology, LTM4600HVIV#PBF Datasheet - Page 9

• Manufacturer Part Number: LTM4600HVIV#PBF
• Description: IC DC/DC UMODULE 10A 104-LGA
• Manufacturer: Linear Technology
• Series: µModuler
• Type: Point of Load (POL) Non-Isolatedr

Specifications of LTM4600HVIV#PBF

• Design Resources: LTM4600HV Spice Model
• Output: 0.6 ~ 5 V
• Number Of Outputs: 1
• Power (watts): 50W
• Mounting Type: Surface Mount
• Voltage - Input: 4.5 ~ 28 V
• Package / Case: 104-LGA
• 1st Output: 0.6 ~ 5 VDC @ 10A
• Size / Dimension: 0.59" L x 0.59" W x 0.11" H (15mm x 15mm x 2.8mm)
• Power (watts) - Rated: 50W
• Operating Temperature: -40°C ~ 85°C
• Efficiency: 92%
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• 3rd Output: -
• 2nd Output: -

APPLICATIO S I FOR ATIO
The typical LTM4600HV application circuit is shown in
Figure 21. External component selection is primarily
determined by the maximum load current and output
voltage.
Output Voltage Programming and Margining
The PWM controller of the LTM4600HV has an internal
0.6V±1% reference voltage. As shown in the block diagram,
a 100k/0.5% internal feedback resistor connects V
and V
SGND pin programs the output voltage:
Table 1 shows the standard values of 1% R
for typical output voltages:
Table 1.
Voltage margining is the dynamic adjustment of the output
voltage to its worst case operating range in production
testing to stress the load circuitry, verify control/protec-
tion functionality of the board and improve the system
reliability. Figure 2 shows how to implement margining
function with the LTM4600HV. In addition to the feedback
resistor R
Turn off both transistor Q
margining. When Q
R
(kΩ)
(V)
V
SET
O
V
O
OSET
=
Figure 2. LTM4600HV Margining Implementation
Open
LTM4600HV
0.6
0 6
PGND
.
SET
pins. Adding a resistor R
V
, several external components are added.
•
100
1.2
100
R
k R
U
UP
SET
66.5
100k
+
1.5
SGND
is on and Q
SET
U
49.9
UP
1.8
V
V
OUT
OSET
and Q
43.2
R
2
DOWN
SET
W
SET
DOWN
from V
31.6
2.5
is off, the output
R
R
DOWN
2N7002
UP
2N7002
to disable the
4600hv F02
Q
Q
SET
22.1
DOWN
UP
OSET
3.3
U
resistor
pin to
13.7
OUT
5
voltage is margined up. The output voltage is margined
down when Q
voltage V
resistor values of R
the following equations:
Input Capacitors
The LTM4600HV μModule should be connected to a low
ac-impedance DC source. High frequency, low ESR input
capacitors are required to be placed adjacent to the mod-
ule. In Figure 21, the bulk input capacitor C
for its ability to handle the large RMS current into the
converter. For a buck converter, the switching duty-cycle
can be estimated as:
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
In the above equation, η% is the estimated effi ciency of
the power module. C1 can be a switcher-rated electrolytic
aluminum capacitor, OS-CON capacitor or high volume
ceramic capacitors. Note the capacitor ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to properly derate the input capacitor,
or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements over temperature.
In Figure 21, the input capacitors are used as high fre-
quency input decoupling capacitors. In a typical 10A
output application, 1-2 pieces of very low ESR X5R or
X7R (for extended temperature range), 10μF ceramic
capacitors are recommended. This decoupling capacitor
D
I
R
(
CIN RMS
R
SET
=
SET
R
(
R
(
SET
V
SET
V
IN
+
O
O
R
(
•
needs to be margined up/down by ±M%, the
UP
100
)
R
V
=
O
UP
)•
DOWN
I
k R
•( – %)
O MAX
V
)
Ω
1
(
η
O
+
%
UP
•(
100
M
DOWN
is on and Q
1
)
and R
+
•
k
M
Ω
%)
D
)
DOWN
•(
=
1
=
0 6
−
.
0 6
LTM4600HV
D
UP
.
V
can be calculated from
)
V
is off. If the output
IN
is selected
4600hvfc
9