CS2082EDWR20 ON Semiconductor, CS2082EDWR20 Datasheet - Page 7

• Manufacturer Part Number: CS2082EDWR20
• Description: IC DRIVR ASIC DUAL AIRBAG 20SOIC
• Manufacturer: ON Semiconductor

Specifications of CS2082EDWR20

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: CS2082EDWR20OS

pulled down to GND through separate nominal 10 k
resistors, thus biasing each normal fire path to about 1/2
V
and SGx bits are set for that path. To detect faults between
fire paths and to test driver function, each driver should be
activated individually. The activated driver should cause its
respective fault bit to be set. If an activated driver does not
set its respective fault bit, a driver fault has been detected. If
an activated driver causes the fault bit of an inactivated
driver to be set, a fault between fire paths has been detected.
Table 4 defines the implied ranges over which the various
types of faults can be detected.
Squib Resistance Measurement – $3d
measurement for the selected firing path. The respective
active–high bit definitions are shown in Table 5. At
power–up, the default path is ‘None.’
(proportional to V
current is passed to an external load resistor at the MR pin,
converting the current back into a voltage. This voltage may
be read directly at the MR pin, or passed through the analog
multiplexer to be read at the A
the squib differential voltage (V
(R
resistance such that:
resistance range of 0.6
Short to Ground
Short to Battery
Open
Driver Open
Driver Shorted
Squib to Squib
BAT
Each SHx pin is pulled up to V
The
Squib resistance is measured by forcing 50 mV nominal
Typical MR voltage response for R
MR
D3
Table 4. Implied Resistive Fault Detection Ranges
x
x
x
x
. An open fire path has been detected if both the SBx
), and the measured MR voltage (V
Fault
$3d
Table 5. Squib Resistance Path Select
D2
x
x
x
x
R SQUIB +
command
CC
D1
0
0
1
1
) across the squib. The resulting squib
Min
1
1
5
1
1
1
to 6.0
R MR
D0
activates
0
1
0
1
OUT
DIFF
Nom
V MR
BAT
20
5
5
5
5
5
pin. The known values of
is illustrated in Figure 2.
NONE
SQUIB 1
SQUIB 2
NONE
) and the MR resistance
V DIFF
MR
while each SLx pin is
= 50
MR
squib
Max
10
10
40
10
10
10
Path
) indicate squib
over a squib
resistance
Unit
k
k
k
k
k
k
http://onsemi.com
CS2082
7
tolerances and with and external 1% load resistor at the MR
pin can be defined by the equation:
where V
values for the squib resistance solution algorithm, R
the actual squib resistance, and R
solution algorithm. An additional error may be added if the
MR voltage is measured through the analog multiplexer.
through the squib to the SLx pin, and returned to ground
through the MR load resistor. Current clamps are provided
for both the SHx and SLx pins and a voltage clamp is
provided for the MR pin. These clamps along with the
resolution of the ADC are the constraining factors for the
minimum and maximum measurable squib resistance
values.
as:
defined as:
differential voltage, I
current limit, V
toleranced MR load resistor value and n is the number of bits
of resolution of the ADC.
faults to GND or BAT (dependent on V
R SQUIB(MAX) +
Measurement accuracy of the CS2082 with combined
In operation, current is sourced from V
The minimum measurable squib resistance can be defined
The maximum measurable squib resistance can be
In the above equations, V
It should be noted that during resistive measurements,
V DIFF(MIN)
I LIM(MAX)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
R SQ(E) +
0.6
Figure 2. Typical MR Voltage Response
DIFF(IDEAL)
v R SQUIB(MIN) v
1.4
CLAMP
+ R SQ(A) )12.5% *15.94%
V DIFF(MAX)
V DIFF(IDEAL)
V DIFF "12%
R SQ(A)
2.2
and R
LIM
is the MR clamp voltage, R
is the SHx resistive measure
R
3.0
MR(IDEAL)
DIFF
" 1%
SQUIB
V DIFF(MIN)
V CC(MIN)
SQ(E)
is the SHx–SLx forced
R MR(MAX)
3.8
V CLAMP(MAX)
R MR(IDEAL)
R MR " 1%
is the result of the
BAT
are the assumed
BAT
4.6
to the SHx pin,
R MR(MIN)
voltage and
(2 n * 1)
MR
5.4
SQ(A)
is the
is