CS2082EDWR20 ON Semiconductor, CS2082EDWR20 Datasheet - Page 6

• Manufacturer Part Number: CS2082EDWR20
• Description: IC DRIVR ASIC DUAL AIRBAG 20SOIC
• Manufacturer: ON Semiconductor

Specifications of CS2082EDWR20

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: CS2082EDWR20OS

diagnostic system for up to two independent firing loops.
Communication with the ASIC is through a synchronous
serial port using Serial Peripheral Interface (SPI) protocol,
at CLK rates up to 2.0 MHz.
received at the D
pins. Error detection logic is included in the SPI to guard
against glitches on either the CS or CLK logic signal inputs.
A valid CS frame must contain exactly 8 CLK cycles for
each CS low–high–low transition. Detection of a frame error
will cause input data for that frame to be ignored and an error
code ($FE) to be sent during the next valid CS frame.
before the rising edge of CLK. The 8 bits sent from D
after CS goes high will be the previous data received, data
from either the status register or the fault register, or the CS
frame error code ($FE).
before the rising edge of CLK. The 8 bits received at D
before CS goes low will be the current command. Table 1
defines the legal 8–bit SPI commands, where d = four data
bits and x = don’t care. All other inputs will be ignored.
Read Status Register – $1x
register to be sent from D
frame. The status register reports the condition of the firing
paths, closure detection of an external safing switch between
PACKAGE PIN DESCRIPTION
The CS2082 is an automotive air bag deployment and
Data is simultaneously sent from the D
The data at D
The data at D
The $1x command causes the data contained in the status
Package Lead Number
COMMAND
Table 1. Valid CS2082 SPI Commands
$Ad
$1x
$2x
$3d
$4d
$5d
$6d
SO–20L
18
19
20
OUT
IN
IN
is received MSB first and must be valid
pin under the control of the CS and CLK
is sent MSB first and is guaranteed valid
Read Staus Register
Read Fault Register
Squib Resistance Measurements
Analog MUX Select
Low Side Switch Control
Auxiliary Control Register
High Side Switch Control
OUT
(continued)
during the next valid CS
FUNCTION
Pin Symbol
Pin Symbol
GND
V
D
CC
IN
FUNCTIONAL DESCRIPTION
OUT
pin and
http://onsemi.com
OUT
IN
Serial Port Input.
5.0 V Regulated Supply.
Signal Ground.
CS2082
6
the V
pump, and the state of external V
supplies. The status register is an 8–bit active–high register
with bit definition as shown in Table 2.
Read Fault Register – $2x
register to be sent from D
frame. The register reports fire path faults by continuously
comparing each path to a portion of the voltage at the V
pin. The fault register is an 8–bit active–high register with
bit definition as shown in Table 3.
The $2x command causes the data contained in the fault
BIT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
RES
Table 2. Status Register Bit Definition
Table 3. Fault Register Bit Definition
and VR1 pins, the state of the internal charge
VALUE
VALUE
SSC
SG2
SG1
SB2
SB1
F1
F2
RL
BL
CL
0
0
0
0
0
0
Function
Function
Always Logic zero
Always Logic zero
SH1 and SL1 switches active
SH2 and SL2 switches active
Safing Sensor is closed
V
V
CHRG voltage is below trip
Always Logic zero
Always Logic zero
Always Logic zero
Always Logic zero
High Side of Sqib 2 above
75% V
High Side of Sqib 1 above
75% V
Low Side of Sqib 2 below
25% V
Low Side of Sqib 1 below
25% V
RES
BAT
voltage is below trip
voltage is below trip
OUT
BAT
BAT
BAT
BAT
DESCRIPTION
DESCRIPTION
trip threshold
trip threshold
trip threshold
trip threshold
during the next valid CS
BAT
and V
RES
power
BAT