HD9P6409-9Z96 Intersil, HD9P6409-9Z96 Datasheet - Page 5

• Manufacturer Part Number: HD9P6409-9Z96
• Description: IC MED MANCHESTER 1MHZ 20-SOIC
• Manufacturer: Intersil
• Type: Manchester Encoder/Decoderr

Specifications of HD9P6409-9Z96

• Applications: Security
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Repeater Operation
Manchester Il data can be presented to the repeater in either
of two ways. The inputs Bipolar One In and Bipolar Zero In
will accept data from differential inputs such as a comparator
or sensed transformer coupled bus. The input Unipolar Data
In accepts only noninverted Manchester II coded data. The
decoder requires a single clock with a frequency 16X or 32X
the desired data rate. This clock is selected to 16X with
Speed Select low and 32X with Speed Select high. For long
data links the 32X mode should be used as this permits a
wider timing jitter margin.
The inputs UDl, or BOl, BZl are delayed approximately 1/2
bit period and repeated as outputs BOO and BZO. The 2X
ECLK is transmitted out of the repeater synchronously with
BOO and BZO.
DCLK
SDO
NVM
RST
UDI
COUNT
INPUT
ECLK
SRST
BOO
BZO
RST
UDI
5
COMMAND
SYNC
SYNC PULSE
1
FIGURE 3. REPEATER OPERATION
FIGURE 2. DECODER OPERATION
1
2
0
0
3
HD-6409
HD-6409
1
0
4
1
A low on CTS enables ECLK, BOO, and BZO. In contrast to
the converter mode, a transition on CTS does not initiate a
synchronization sequence of eight 0’s and a command sync.
The repeater mode does recognize a command or data sync
pulse. SD/CDS is an output which reflects the state of the
most recent sync pulse received, with high indicating a
command sync and low indicating a data sync.
When RST is low, the outputs SDO, DCLK, and NVM are
low, and SRST is set low. SRST remains low after RST goes
high and is not reset until a sync pulse and two valid
manchester bits are received with the reset bit low. The reset
bit is the first data bit after the sync pulse. With RST high,
NRZ Data is transmitted out of Serial Data Out
synchronously with the 1X DCLK.
0
5
1
0
6
1
0
7
1
0
October 15, 2008
FN2951.3