HD9P6409-9Z96 Intersil, HD9P6409-9Z96 Datasheet - Page 3

• Manufacturer Part Number: HD9P6409-9Z96
• Description: IC MED MANCHESTER 1MHZ 20-SOIC
• Manufacturer: Intersil
• Type: Manchester Encoder/Decoderr

Specifications of HD9P6409-9Z96

• Applications: Security
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
NOTE: (I) Input
NUMBER
PIN
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
TYPE
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
(O) Output
SYMBOL
SD/CDS
SRST
DCLK
ECLK
SDO
NVM
GND
BOO
RST
CTS
BZO
V
UDI
BOl
BZl
C
MS
O
SS
I
CC
X
O
X
3
Bipolar Zero Input
Bipolar One Input
Unipolar Data Input
Serial Data/Command
Data Sync
Serial Data Out
Serial Reset
Nonvalid Manchester
Decoder Clock
Reset
Ground
Clock Output
Clock Input
Clock Drive
Mode Select
Clear to Send
Encoder Clock
Speed Select
Bipolar Zero Output
Bipolar One Out
V
CC
NAME
Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II encoded
data to the decoder, BZI and BOl are logical complements. When using pin 3, Unipolar
Data Input (UDI) for data input, BZI must be held high.
Used in conjunction with pin 1, Bipolar Zero Input (BZI), to input Manchester II encoded
data to the decoder, BOI and BZI are logical complements. When using pin 3, Unipolar
Data Input (UDI) for data input, BOl must be held low.
An alternate to bipolar input (BZl, BOl), Unipolar Data Input (UDl) is used to input
Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2 (BOl) for
data input, UDI must be held low.
In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ data is
accepted synchronously on the falling edge of encoder clock output (ECLK). In the
repeater mode, SD/CDS is an output indicating the status of last valid sync pattern
received. A high indicates a command sync and a low indicates a data sync pattern.
The decoded serial NRZ data is transmitted out synchronously with the decoder clock
(DCLK). SDO is forced low when RST is low.
In the converter mode, SRST follows RST. In the repeater mode, when RST goes low,
SRST goes low and remains low after RST goes high. SRST goes high only when RST
is high, the reset bit is zero, and a valid synchronization sequence is received.
A low on NVM indicates that the decoder has received invalid Manchester data and
present data on Serial Data Out (SDO) is invalid. A high indicates that the sync pulse and
data were valid and SDO is valid. NVM is set low by a low on RST, and remains low after
RST goes high until valid sync pulse followed by two valid Manchester bits is received.
The decoder clock is a 1X clock recovered from BZl and BOl, or UDI to synchronously
output received NRZ data (SDO).
In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low. A high on
RST enables SDO and DCLK, and forces SRST high. NVM remains low after RST goes
high until a valid sync pulse followed by two Manchester bits is received, after which it
goes high. In the repeater mode, RST has the same effect on SDO, DCLK and NVM as
in the converter mode. When RST goes low, SRST goes low and remains low after RST
goes high. SRST goes high only when RST is high, the reset bit is zero and a valid
synchronization sequence is received.
Ground
Buffered output of clock input I
I
for the connection of the crystal.
If the internal oscillator is used, O
MS must be held low for operation in the converter mode, and high for operation in the
repeater mode.
In the converter mode, a high disables the encoder, forcing outputs BOO, BZO high and
ECLK low. A high to low transition of CTS initiates transmission of a Command sync pulse.
A low on CTS enables BOO, BZO, and ECLK. In the repeater mode, the function of CTS
is identical to that of the converter mode with the exception that a transition of CTS does
not initiate a synchronization sequence.
In the converter mode, ECLK is a 1X clock output used to receive serial NRZ data to
SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from BZl and BOl
data by the digital phase locked loop.
A logic high on SS sets the data rate at 1/32 times the clock frequency while a low sets
the data rate at 1/16 times the clock frequency.
BZO and its logical complement BOO are the Manchester data outputs of the encoder.
The inactive state for these outputs is in the high state.
See pin 18.
V
(pin 10) is recommended.
X
CC
is the input for an external clock or, if the internal oscillator is used, I
is the +5V power supply pin. A 0.1µF decoupling capacitor from V
HD-6409
HD-6409
X
. May be used as clock signal for other peripherals.
X
and I
DESCRIPTION
X
are used for the connection of the crystal.
CC
X
and O
(pin 20) to GND
October 15, 2008
X
are used
FN2951.3