IDT72P51559L6BBI8 IDT, Integrated Device Technology Inc, IDT72P51559L6BBI8 Datasheet - Page 76

• Manufacturer Part Number: IDT72P51559L6BBI8
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51559L6BBI8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51559L6BBI8

Device 5 PAEn
Cycle:
*A*
*AA* Queue 24 of Device 5 is selected for read operations.
*B*
*BB* Current Word is kept on the output bus since REN is HIGH.
*C*
*CC* Word Wa+1 of D5 Q17 is read due to FWFT.
*D*
*DD* Word, Wy from the newly selected queue, Q24 will be read out due to FWFT operation.
*E*
*EE* Word, Wy+1 is read from Q24 of D5.
*F*
*FF* Word, Wy+2 is read from Q24 of D5.
*G*
*GG* The PAEn bus updates to show that Q24 of D5 is almost empty based on the reading out of word, Wy+1.
IDT72P51539/72P51549/72P51559/72P51569 1.8V, MQ FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
Device 5 PAE
Device 5 -Qn
Prev PAEn
Bus PAEn
WRADD
WADEN
RDADD
Queue 24 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
A status word from another device has control of the PAEn bus.
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
Word Wp+1 is written into the previously selected queue.
Word Wp+2 is written into the previously selected queue.
Word, Wn is written into the newly selected queue, Q24 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
t
Status word 4 of Device 5 is selected on the PAEn bus. Q24 of device 5 will therefore have is PAE status output on PAE[0]. There is a single RCLK cycle latency before
the PAEn bus changes to the new selection.
Queue 8 of Device 3 is selected for write operations.
Word Wn+1 is written into Q24 of D5.
No writes occur.
The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and status word 4 is placed onto the outputs. The device of the previously selected
status word now places its PAEn outputs into High-Impedance to prevent bus contention.
The discrete PAE flag will go HIGH to show that Q24 of D5 is not almost empty. Q24 of device 5 will have its PAE status output on PAE[0].
Status word 3 of device 4 is selected on the write port for the PAFn bus.
The discrete PAE flag goes LOW to show that Q24 of D5 is almost empty based on the reading of Wy+1.
RADEN
SKEW3
WCLK
ESTR
FSTR
RCLK
REN
WEN
Dn
+ RCLK + t
RAE
t
t
ENS
QS
t
AS
(if t
t
QS
101 11000
D5Q24
Previous value loaded on to PAE bus
D5 Q17 Status
Previous value loaded on to PAE bus
SKEW3
t
Wp
AS
*A*
Writes to Previous Q
101 11000
D5Q24
*AA*
is violated one extra RCLK cycle will be added).
t
t
AH
QH
t
t
AH
DS
D5 Q17
t
Wp+1
QH
Wa
*B*
1
*BB*
t
DH
Figure 64. PAE
t
DS
Wp+2
*C*
2
PAE
PAE
PAE
PAE n - Direct Mode, Flag Operation
*CC*
t
DH
t
SKEW3
t
A
t
DS
t
Wp+3
STS
t
AS
*D*
3
76
Wa+1
101 00011
D5 SW 3
D5 Q17
*DD*
t
DH
t
t
A
QS
t
AS
t
t
011 01000
t
AH
t
RAE
D5Q24
STH
ENS
D5 Q24
D3Q8
Wn
status
*E*
Wy
D5 Q24
*EE*
t
t
AH
t
QH
t
ENH
A
t
PAEZL
*F*
Wy+1
D5 Q24
*FF*
t
STS
t
A
COMMERCIAL AND INDUSTRIAL
t
AS
100 00100
t
t
RAE
PAEHZ
D4 SW 2
*G*
D5 SW 3
xxxx xxx1
D5 SW 3
xxxx xxx1
TEMPERATURE RANGES
Wy+2
D5 Q24
*GG*
t
AH
t
FEBRUARY 13, 2009
STH
t
A
t
PAE
t
ENH
t
RAE
*H*
Wy+3
D5 Q24
xxxx xxx0
D5 SW 3
D5 SW 3
xxxx xxx0
6715 drw72