IDT72P51559L6BBI8 IDT, Integrated Device Technology Inc, IDT72P51559L6BBI8 Datasheet - Page 2

• Manufacturer Part Number: IDT72P51559L6BBI8
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51559L6BBI8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51559L6BBI8

Features ........................................................................................................................................................................................................................ 1
Description ................................................................................................................................................................................................................... 5
Pin configuration ......................................................................................................................................................................................................... 7
Detailed Description .................................................................................................................................................................................................... 8
Pin Descriptions ......................................................................................................................................................................................................... 10
Pin number table ........................................................................................................................................................................................................ 16
Recommended DC operating conditions ................................................................................................................................................................ 17
Absolute maximum ratings ........................................................................................................................................................................................ 17
DC electrical characteristics ..................................................................................................................................................................................... 18
AC electrical characteristics ...................................................................................................................................................................................... 20
Functional description .............................................................................................................................................................................................. 22
Queue Description ..................................................................................................................................................................................................... 25
Flag Description ......................................................................................................................................................................................................... 42
JTAG Interface ............................................................................................................................................................................................................ 82
JTAG AC electrical characteristics ............................................................................................................................................................................ 86
Ordering Information ................................................................................................................................................................................................. 87
Table 1 — Device programming mode comparison ........................................................................................................................................................ 22
Table 2 — Setting the queue programming mode during master reset ............................................................................................................................. 22
Table 3 — Mode Configuration ...................................................................................................................................................................................... 25
Table 4 — Write Address Bus, WRADD[7:0] ................................................................................................................................................................... 26
Table 5 — Read Address Bus, RDADD[7:0] .................................................................................................................................................................. 27
Table 6 — Write Queue Switch Operation ...................................................................................................................................................................... 30
Table 7 — Read Queue Switch Operation ..................................................................................................................................................................... 32
Table 8 — Same Queue Switch ..................................................................................................................................................................................... 32
Table 9 — Flag operation boundaries and Timing .......................................................................................................................................................... 45
Table 10 — Packet Mode Valid Byte for x36 bit word configuration ................................................................................................................................. 48
Table 11 — Bus-Matching Set-Up .................................................................................................................................................................................. 52
IDT72P51539/72P51549/72P51559/72P51569 1.8V, MQ FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
Serial Programming .............................................................................................................................................................................................. 23
Default Programming ............................................................................................................................................................................................ 23
Parallel Programming ........................................................................................................................................................................................... 23
Configuration of the IDT Multi-queue flow-control device ....................................................................................................................................... 25
Standard mode operation ..................................................................................................................................................................................... 26
Read Queue Selection and Read Operation ......................................................................................................................................................... 27
Switching Queues on the Write Port ...................................................................................................................................................................... 29
Switching Queues on the Read Port ..................................................................................................................................................................... 31
PAFn Flag Bus Operation ..................................................................................................................................................................................... 42
Full Flag Operation ............................................................................................................................................................................................... 42
Empty or Output Ready Flag Operation (EF/OR) .................................................................................................................................................. 42
Almost Full Flag .................................................................................................................................................................................................... 43
Almost Empty Flag ................................................................................................................................................................................................ 43
Packet Ready Flag ............................................................................................................................................................................................... 47
Packet Mode Demarcation bits .............................................................................................................................................................................. 49
Table of Contents
List of Tables
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009