IDT89HPES12T3G2ZABC IDT, Integrated Device Technology Inc, IDT89HPES12T3G2ZABC Datasheet - Page 7

• Manufacturer Part Number: IDT89HPES12T3G2ZABC
• Description: IC PCI SW 12LANE 3PORT 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES12T3G2ZABC

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES12T3G2ZABC

IDT 89HPES12T3G2 Data Sheet
JTAG_TRST_N
JTAG_TDO
JTAG_TMS
V
REFRES0
REFRES2
REFRES4
V
V
Signal
Signal
V
DD
V
DD
DD
DD
DD
V
CORE
PEHA
PETA
SS
PEA
I/O
Type
Type
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
Table 7 Power, Ground, and SerDes Resistor Pins
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
Port 0 External Reference Resistor. Provides a reference for the Port 0
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
Port 2 External Reference Resistor. Provides a reference for the Port 2
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
Port 4 External Reference Resistor. Provides a reference for the Port 4
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
Core V
I/O V
PCI Express Analog Power. Serdes analog power supply (1.0V).
PCI Express Analog High Power. Serdes analog power supply (2.5V).
PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
Ground.
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins (Part 2 of 2)
DD.
DD.
LVTTL I/O buffer power supply.
Power supply for core logic.
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Name/Description
Name/Description
September 13, 2010