IDT89HPES12T3G2ZABC IDT, Integrated Device Technology Inc, IDT89HPES12T3G2ZABC Datasheet - Page 4

• Manufacturer Part Number: IDT89HPES12T3G2ZABC
• Description: IC PCI SW 12LANE 3PORT 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES12T3G2ZABC

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES12T3G2ZABC

Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES12T3G2 Data Sheet
The following tables list the functions of the pins provided on the PES12T3G2. Some of the functions listed may be multiplexed onto the same pin.
Note: In the PES12T3G2, the two downstream ports are labeled port 2 and port 4.
SSMBADDR[5,3:1]
MSMBADDR[4:1]
PEREFCLKP[0]
PEREFCLKN[0]
PE0RN[3:0]
PE2RN[3:0]
PE4RN[3:0]
PE0RP[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE2RP[3:0]
PE2TP[3:0]
PE2TN[3:0]
PE4RP[3:0]
PE4TP[3:0]
PE4TN[3:0]
MSMBCLK
MSMBDAT
REFCLKM
SSMBCLK
SSMBDAT
Signal
Signal
Type
Type
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I
I
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
This pin should be static and not change following the negation of
PERSTN.
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 2 PCI Express Interface Pins
Table 3 SMBus Interface Pins
4 of 30
Name/Description
Name/Description
September 13, 2010