IDT89HPES6T6G2ZCALG8 IDT, Integrated Device Technology Inc, IDT89HPES6T6G2ZCALG8 Datasheet - Page 5

• Manufacturer Part Number: IDT89HPES6T6G2ZCALG8
• Description: IC PCI SW 6LANE 6PORT 324-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES6T6G2ZCALG8

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES6T6G2ZCALG8

IDT 89HPES6T6G2 Data Sheet
SWMODE[2:0]
JTAG_TCK
JTAG_TDO
JTAG_TMS
JTAG_TDI
GPIO[10]
Signal
Signal
CCLKDS
CCLKUS
PERSTN
Signal
GPIO[8]
GPIO[9]
Type
Type
Type
I/O
I/O
I/O
O
I
I
I
I
I
I
I
Table 3 General Purpose I/O Pins (Part 2 of 2)
General Purpose I/O.
General Purpose I/O.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P1RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 1
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P5RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 5
Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be overridden by modifying the SCLK bit in each downstream
port’s PCIELSTS register.
Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by mod-
ifying the SCLK bit in the P0_PCIELSTS register.
Fundamental Reset. Assertion of this signal resets all logic inside
PES6T6G2 and initiates a PCI Express fundamental reset.
Switch Mode. These configuration pins determine the PES6T6G2 switch
operating mode.
0x0 -Normal switch mode
0x1 -Normal switch mode with Serial EEPROM initialization
0x2 - through 0x7 Reserved
These pins should be static and not change following the negation of
PERSTN.
JTAG Clock. This is an input test clock used to clock the shifting of data into
or out of the boundary scan logic or JTAG Controller. JTAG_TCK is indepen-
dent of the system clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
Table 5 Test Pins (Part 1 of 2)
Table 4 System Pins
5 of 29
Name/Description
Name/Description
Name/Description
September 13, 2010