IDT89HPES6T6G2ZCALG8 IDT, Integrated Device Technology Inc, IDT89HPES6T6G2ZCALG8 Datasheet - Page 3

• Manufacturer Part Number: IDT89HPES6T6G2ZCALG8
• Description: IC PCI SW 6LANE 6PORT 324-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES6T6G2ZCALG8

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES6T6G2ZCALG8

Hot-Plug Interface
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES6T6G2 generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES6T6G2. In response to an I/O expander interrupt, the PES6T6G2 generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
may be configured independently as an input or output through software control. All GPIO pins are shared with other on-chip functions. These alter-
nate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES6T6G2 Data Sheet
The PES6T6G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES6T6G2
The PES6T6G2 provides 7 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
The following tables list the functions of the pins provided on the PES6T6G2. Some of the functions listed may be multiplexed onto the same pin.
PES6T6G2
(a) Unified Configuration and Management Bus
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
PE0RP[0]
PE0RN[0]
PE0TN[0]
PE1RP[0]
PE1RN[0]
PE1TN[0]
PE2RP[0]
PE2RN[0]
PE2TN[0]
PE3RP[0]
PE3RN[0]
PE3TN[0]
PE0TP[0]
PE1TP[0]
PE2TP[0]
PE3TP[0]
Signal
Processor
SMBus
Master
Type
EEPROM
Figure 3 SMBus Interface Configuration Examples
Serial
Table 1 PCI Express Interface Pins (Part 1 of 2)
O
O
O
O
I
I
I
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pair for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit
pair for port 0. Port 0 is the upstream port.
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pair for port 1.
PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit
pair for port 1.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pair for port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit
pair for port 2.
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit
pair for port 3.
...
Devices
SMBus
Other
3 of 29
Name/Description
(b) Split Configuration and Management Buses
PES6T6G2
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Processor
SMBus
Master
EEPROM
Serial
...
Devices
SMBus
Other
September 13, 2010