KSZ8695PX Micrel Inc, KSZ8695PX Datasheet - Page 27

• Manufacturer Part Number: KSZ8695PX
• Description: IC SWITCH 10/100 1PORT 289PBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8695PX

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 289-PBGA
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: KSZ8695PX-EVAL - EVAL KIT EXPERIMENT ONLY KSZ8695
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1024

KS8695PX
General Purpose I/O Pins (continued)
Note:
1. I = Input.
M9999-091605
O = Output.
I/O = Bidirectional.
C15
C15
C15
C15
C15
A15
A15
A15
A15
A15
A16
A16
A16
A16
A16
D14
D14
D14
D14
D14
D10
D10
D10
D10
D10
C10
C10
C10
C10
C10
C11
C11
C11
C11
C11
D11
D11
D11
D11
D11
A10
A10
A10
A10
A10
A11
A11
A11
A11
A11
B11
B11
B11
B11
B11
Pin
Pin
Pin
A6
A6
A6
A6
A6
B9
B9
B9
B9
B9
C8
C8
C8
C8
C8
A9
A9
A9
A9
A9
D7
D7
D7
D7
D7
E4
E4
E4
E4
E4
DEVSELN
DEVSELN
DEVSELN
DEVSELN
DEVSELN
FRAMEN
FRAMEN
FRAMEN
FRAMEN
FRAMEN
TRDYN
TRDYN
TRDYN
TRDYN
TRDYN
STOPN
STOPN
STOPN
STOPN
STOPN
PERRN
PERRN
PERRN
PERRN
PERRN
SERRN
SERRN
SERRN
SERRN
SERRN
CBEN3
CBEN3
CBEN3
CBEN3
CBEN3
CBEN2
CBEN2
CBEN2
CBEN2
CBEN2
CBEN1
CBEN1
CBEN1
CBEN1
CBEN1
CBEN0
CBEN0
CBEN0
CBEN0
CBEN0
M66EN
M66EN
M66EN
M66EN
M66EN
IRDYN
IRDYN
IRDYN
IRDYN
IRDYN
IDSEL
IDSEL
IDSEL
IDSEL
IDSEL
Name
Name
Name
PAD2
PAD2
PAD2
PAD2
PAD2
PAD1
PAD1
PAD1
PAD1
PAD1
PAD0
PAD0
PAD0
PAD0
PAD0
PAR
PAR
PAR
PAR
PAR
I/O Type
I/O Type
I/O Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
(1)
Description
Description
32-Bit PCI address and data (continued from previous page).
32-Bit PCI address and data (continued from previous page).
32-Bit PCI address and data (continued from previous page).
32-Bit PCI address and data (continued from previous page).
32-Bit PCI address and data (continued from previous page).
PCI commands and byte enable. Active low.
PCI commands and byte enable. Active low.
PCI commands and byte enable. Active low.
PCI commands and byte enable. Active low.
PCI commands and byte enable. Active low.
The PCI command and byte enable signals are multiplexed on the same pins. During
The PCI command and byte enable signals are multiplexed on the same pins. During
The PCI command and byte enable signals are multiplexed on the same pins. During
The PCI command and byte enable signals are multiplexed on the same pins. During
The PCI command and byte enable signals are multiplexed on the same pins. During
the fi rst clock cycle of a PCI transaction, the CBEN bus contains the command for
the fi rst clock cycle of a PCI transaction, the CBEN bus contains the command for
the fi rst clock cycle of a PCI transaction, the CBEN bus contains the command for
the fi rst clock cycle of a PCI transaction, the CBEN bus contains the command for
the fi rst clock cycle of a PCI transaction, the CBEN bus contains the command for
the transaction. The PCI transaction consists of the address phases and one or more
the transaction. The PCI transaction consists of the address phases and one or more
the transaction. The PCI transaction consists of the address phases and one or more
the transaction. The PCI transaction consists of the address phases and one or more
the transaction. The PCI transaction consists of the address phases and one or more
data phases. During the data phases of the transaction, the bus carries the byte
data phases. During the data phases of the transaction, the bus carries the byte
data phases. During the data phases of the transaction, the bus carries the byte
data phases. During the data phases of the transaction, the bus carries the byte
data phases. During the data phases of the transaction, the bus carries the byte
enable for the current data phases.
enable for the current data phases.
enable for the current data phases.
enable for the current data phases.
enable for the current data phases.
Parity. PCI bus parity is even across PAD[31:0] and CBEN[3:0]. The KS8695PX
Parity. PCI bus parity is even across PAD[31:0] and CBEN[3:0]. The KS8695PX
Parity. PCI bus parity is even across PAD[31:0] and CBEN[3:0]. The KS8695PX
Parity. PCI bus parity is even across PAD[31:0] and CBEN[3:0]. The KS8695PX
Parity. PCI bus parity is even across PAD[31:0] and CBEN[3:0]. The KS8695PX
generates PAR during the address phase and write data phases as a bus master and
generates PAR during the address phase and write data phases as a bus master and
generates PAR during the address phase and write data phases as a bus master and
generates PAR during the address phase and write data phases as a bus master and
generates PAR during the address phase and write data phases as a bus master and
during read data phases as a target. It checks for correct PAR during the read data
during read data phases as a target. It checks for correct PAR during the read data
during read data phases as a target. It checks for correct PAR during the read data
during read data phases as a target. It checks for correct PAR during the read data
during read data phases as a target. It checks for correct PAR during the read data
phase as a bus master, during every address phase as a bus slave, and during write
phase as a bus master, during every address phase as a bus slave, and during write
phase as a bus master, during every address phase as a bus slave, and during write
phase as a bus master, during every address phase as a bus slave, and during write
phase as a bus master, during every address phase as a bus slave, and during write
data phases as a target.
data phases as a target.
data phases as a target.
data phases as a target.
data phases as a target.
PCI bus frame signal. Active low. FRAMEN is an indication of an active PCI bus
PCI bus frame signal. Active low. FRAMEN is an indication of an active PCI bus
PCI bus frame signal. Active low. FRAMEN is an indication of an active PCI bus
PCI bus frame signal. Active low. FRAMEN is an indication of an active PCI bus
PCI bus frame signal. Active low. FRAMEN is an indication of an active PCI bus
cycle. It is asserted at the beginning of a PCI transaction, i.e. the address phase, and
cycle. It is asserted at the beginning of a PCI transaction, i.e. the address phase, and
cycle. It is asserted at the beginning of a PCI transaction, i.e. the address phase, and
cycle. It is asserted at the beginning of a PCI transaction, i.e. the address phase, and
cycle. It is asserted at the beginning of a PCI transaction, i.e. the address phase, and
deasserted before the fi nal transfer of the data phase of the transaction.
deasserted before the fi nal transfer of the data phase of the transaction.
deasserted before the fi nal transfer of the data phase of the transaction.
deasserted before the fi nal transfer of the data phase of the transaction.
deasserted before the fi nal transfer of the data phase of the transaction.
PCI initiator ready signal. Active low. This signal is asserted by a PCI master to
PCI initiator ready signal. Active low. This signal is asserted by a PCI master to
PCI initiator ready signal. Active low. This signal is asserted by a PCI master to
PCI initiator ready signal. Active low. This signal is asserted by a PCI master to
PCI initiator ready signal. Active low. This signal is asserted by a PCI master to
indicate a valid data phase on the PAD bus during data phases of a write transaction.
indicate a valid data phase on the PAD bus during data phases of a write transaction.
indicate a valid data phase on the PAD bus during data phases of a write transaction.
indicate a valid data phase on the PAD bus during data phases of a write transaction.
indicate a valid data phase on the PAD bus during data phases of a write transaction.
During a read transaction, it indicates that the master is ready to accept data from the
During a read transaction, it indicates that the master is ready to accept data from the
During a read transaction, it indicates that the master is ready to accept data from the
During a read transaction, it indicates that the master is ready to accept data from the
During a read transaction, it indicates that the master is ready to accept data from the
target. A target monitors the IRDYN signal when a data phase is completed on any
target. A target monitors the IRDYN signal when a data phase is completed on any
target. A target monitors the IRDYN signal when a data phase is completed on any
target. A target monitors the IRDYN signal when a data phase is completed on any
target. A target monitors the IRDYN signal when a data phase is completed on any
rising edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles
rising edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles
rising edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles
rising edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles
rising edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles
are inserted until both IRDYN and TRDYN are asserted together.
are inserted until both IRDYN and TRDYN are asserted together.
are inserted until both IRDYN and TRDYN are asserted together.
are inserted until both IRDYN and TRDYN are asserted together.
are inserted until both IRDYN and TRDYN are asserted together.
PCI target ready signal. Active low. This signal is asserted by a PCI slave to
PCI target ready signal. Active low. This signal is asserted by a PCI slave to
PCI target ready signal. Active low. This signal is asserted by a PCI slave to
PCI target ready signal. Active low. This signal is asserted by a PCI slave to
PCI target ready signal. Active low. This signal is asserted by a PCI slave to
indicate a valid data phase on the PAD bus during a read transaction. During a write
indicate a valid data phase on the PAD bus during a read transaction. During a write
indicate a valid data phase on the PAD bus during a read transaction. During a write
indicate a valid data phase on the PAD bus during a read transaction. During a write
indicate a valid data phase on the PAD bus during a read transaction. During a write
transaction, it indicates that the slave is ready to accept data from the target. A PCI
transaction, it indicates that the slave is ready to accept data from the target. A PCI
transaction, it indicates that the slave is ready to accept data from the target. A PCI
transaction, it indicates that the slave is ready to accept data from the target. A PCI
transaction, it indicates that the slave is ready to accept data from the target. A PCI
initiator monitors the TRDYN signal when a data phase is completed on any rising
initiator monitors the TRDYN signal when a data phase is completed on any rising
initiator monitors the TRDYN signal when a data phase is completed on any rising
initiator monitors the TRDYN signal when a data phase is completed on any rising
initiator monitors the TRDYN signal when a data phase is completed on any rising
edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles are
edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles are
edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles are
edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles are
edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles are
inserted until both IRDYN and TRDYN are asserted together.
inserted until both IRDYN and TRDYN are asserted together.
inserted until both IRDYN and TRDYN are asserted together.
inserted until both IRDYN and TRDYN are asserted together.
inserted until both IRDYN and TRDYN are asserted together.
PCI device select signal. Active low. This signal is asserted when the KS8695PX is
PCI device select signal. Active low. This signal is asserted when the KS8695PX is
PCI device select signal. Active low. This signal is asserted when the KS8695PX is
PCI device select signal. Active low. This signal is asserted when the KS8695PX is
PCI device select signal. Active low. This signal is asserted when the KS8695PX is
selected as a target during a bus transaction. When the KS8695PX is the initiator of
selected as a target during a bus transaction. When the KS8695PX is the initiator of
selected as a target during a bus transaction. When the KS8695PX is the initiator of
selected as a target during a bus transaction. When the KS8695PX is the initiator of
selected as a target during a bus transaction. When the KS8695PX is the initiator of
the current bus access, it expects the target to assert DEVSELN within fi ve PCI bus
the current bus access, it expects the target to assert DEVSELN within fi ve PCI bus
the current bus access, it expects the target to assert DEVSELN within fi ve PCI bus
the current bus access, it expects the target to assert DEVSELN within fi ve PCI bus
the current bus access, it expects the target to assert DEVSELN within fi ve PCI bus
cycles, confi rming the access. If the target does not assert DEVSELN within the
cycles, confi rming the access. If the target does not assert DEVSELN within the
cycles, confi rming the access. If the target does not assert DEVSELN within the
cycles, confi rming the access. If the target does not assert DEVSELN within the
cycles, confi rming the access. If the target does not assert DEVSELN within the
required bus cycles, the KS8695PX aborts the bus cycle. To meet the timing require-
required bus cycles, the KS8695PX aborts the bus cycle. To meet the timing require-
required bus cycles, the KS8695PX aborts the bus cycle. To meet the timing require-
required bus cycles, the KS8695PX aborts the bus cycle. To meet the timing require-
required bus cycles, the KS8695PX aborts the bus cycle. To meet the timing require-
ment, the KS8695PX asserts this signal in a medium speed decode timing. ( two bus
ment, the KS8695PX asserts this signal in a medium speed decode timing. ( two bus
ment, the KS8695PX asserts this signal in a medium speed decode timing. ( two bus
ment, the KS8695PX asserts this signal in a medium speed decode timing. ( two bus
ment, the KS8695PX asserts this signal in a medium speed decode timing. ( two bus
cycles).
cycles).
cycles).
cycles).
cycles).
Initialization device select. Active high. It is used as a chip select during confi gura-
Initialization device select. Active high. It is used as a chip select during confi gura-
Initialization device select. Active high. It is used as a chip select during confi gura-
Initialization device select. Active high. It is used as a chip select during confi gura-
Initialization device select. Active high. It is used as a chip select during confi gura-
tion read and write transactions.
tion read and write transactions.
tion read and write transactions.
tion read and write transactions.
tion read and write transactions.
PCI stop signal. Active low. This signal is asserted by the PCI target to indicate to
PCI stop signal. Active low. This signal is asserted by the PCI target to indicate to
PCI stop signal. Active low. This signal is asserted by the PCI target to indicate to
PCI stop signal. Active low. This signal is asserted by the PCI target to indicate to
PCI stop signal. Active low. This signal is asserted by the PCI target to indicate to
the bus master that it is terminating the current transaction. The KS8695PX responds
the bus master that it is terminating the current transaction. The KS8695PX responds
the bus master that it is terminating the current transaction. The KS8695PX responds
the bus master that it is terminating the current transaction. The KS8695PX responds
the bus master that it is terminating the current transaction. The KS8695PX responds
to the assertion of STOPN when it is the bus master, either to disconnect, retry, or
to the assertion of STOPN when it is the bus master, either to disconnect, retry, or
to the assertion of STOPN when it is the bus master, either to disconnect, retry, or
to the assertion of STOPN when it is the bus master, either to disconnect, retry, or
to the assertion of STOPN when it is the bus master, either to disconnect, retry, or
abort the transaction.
abort the transaction.
abort the transaction.
abort the transaction.
abort the transaction.
PCI parity error signal. Active low. The KS8695PX asserts PERRN when it checks
PCI parity error signal. Active low. The KS8695PX asserts PERRN when it checks
PCI parity error signal. Active low. The KS8695PX asserts PERRN when it checks
PCI parity error signal. Active low. The KS8695PX asserts PERRN when it checks
PCI parity error signal. Active low. The KS8695PX asserts PERRN when it checks
and detects a bus parity error. When it generates the PAR output, the KS8695PX
and detects a bus parity error. When it generates the PAR output, the KS8695PX
and detects a bus parity error. When it generates the PAR output, the KS8695PX
and detects a bus parity error. When it generates the PAR output, the KS8695PX
and detects a bus parity error. When it generates the PAR output, the KS8695PX
monitors for any reported parity error on PERRN. When the KS8695PX is the bus
monitors for any reported parity error on PERRN. When the KS8695PX is the bus
monitors for any reported parity error on PERRN. When the KS8695PX is the bus
monitors for any reported parity error on PERRN. When the KS8695PX is the bus
monitors for any reported parity error on PERRN. When the KS8695PX is the bus
master and a parity error is detected, the KS8695PX sets error bits in the control
master and a parity error is detected, the KS8695PX sets error bits in the control
master and a parity error is detected, the KS8695PX sets error bits in the control
master and a parity error is detected, the KS8695PX sets error bits in the control
master and a parity error is detected, the KS8695PX sets error bits in the control
status registers. It completes the current data burst transaction, and then stops the
status registers. It completes the current data burst transaction, and then stops the
status registers. It completes the current data burst transaction, and then stops the
status registers. It completes the current data burst transaction, and then stops the
status registers. It completes the current data burst transaction, and then stops the
operation. After the host clears the system error, the KS8695PX continues its
operation. After the host clears the system error, the KS8695PX continues its
operation. After the host clears the system error, the KS8695PX continues its
operation. After the host clears the system error, the KS8695PX continues its
operation. After the host clears the system error, the KS8695PX continues its
operation.
operation.
operation.
operation.
operation.
PCI system error signal. Active low. If an address parity error is detected, the
PCI system error signal. Active low. If an address parity error is detected, the
PCI system error signal. Active low. If an address parity error is detected, the
PCI system error signal. Active low. If an address parity error is detected, the
PCI system error signal. Active low. If an address parity error is detected, the
KS8695PX asserts the SERRN signal two clocks after the failing address.
KS8695PX asserts the SERRN signal two clocks after the failing address.
KS8695PX asserts the SERRN signal two clocks after the failing address.
KS8695PX asserts the SERRN signal two clocks after the failing address.
KS8695PX asserts the SERRN signal two clocks after the failing address.
PCI 66MHz enable. When asserted, this signal indicates the PCI bus segment is
PCI 66MHz enable. When asserted, this signal indicates the PCI bus segment is
PCI 66MHz enable. When asserted, this signal indicates the PCI bus segment is
PCI 66MHz enable. When asserted, this signal indicates the PCI bus segment is
PCI 66MHz enable. When asserted, this signal indicates the PCI bus segment is
operating at 66MHz. This pin is mainly used in guest bridge mode when the PCLK is
operating at 66MHz. This pin is mainly used in guest bridge mode when the PCLK is
operating at 66MHz. This pin is mainly used in guest bridge mode when the PCLK is
operating at 66MHz. This pin is mainly used in guest bridge mode when the PCLK is
operating at 66MHz. This pin is mainly used in guest bridge mode when the PCLK is
driven by an external host bridge.
driven by an external host bridge.
driven by an external host bridge.
driven by an external host bridge.
driven by an external host bridge.
27
September 2005
Micrel