KSZ8695PX Micrel Inc, KSZ8695PX Datasheet - Page 23

• Manufacturer Part Number: KSZ8695PX
• Description: IC SWITCH 10/100 1PORT 289PBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8695PX

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 289-PBGA
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: KSZ8695PX-EVAL - EVAL KIT EXPERIMENT ONLY KSZ8695
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1024

KS8695PX
Signal Descriptions by Group
Clock and Reset Pins
JTAG Interface Pins
WAN Ethernet Physical Interface Pins
Note:
1. I = Input.
M9999-091605
O = Output.
O/I = Output in normal mode; input pin during reset.
M15
M15
M15
M15
M15
G14
G14
G14
G14
G14
G15
G15
G15
G15
G15
A17
A17
A17
A17
A17
U17
U17
U17
U17
U17
T17
T17
T17
T17
T17
F14
F14
F14
F14
F14
F15
F15
F15
F15
F15
F16
F16
F16
F16
F16
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
G1
G1
G1
G1
G1
G2
G2
G2
G2
G2
G3
G3
G3
G3
G3
G4
G4
G4
G4
G4
G5
G5
G5
G5
G5
E1
E1
E1
E1
E1
E2
E2
E2
E2
E2
CPUCLKSEL
CPUCLKSEL
CPUCLKSEL
CPUCLKSEL
CPUCLKSEL
WANFXSD
WANFXSD
WANFXSD
WANFXSD
WANFXSD
WRSTPLS
WRSTPLS
WRSTPLS
WRSTPLS
WRSTPLS
WANRXM
WANRXM
WANRXM
WANRXM
WANRXM
WANTXM
WANTXM
WANTXM
WANTXM
WANTXM
WANTXP
WANTXP
WANTXP
WANTXP
WANTXP
WANRXP
WANRXP
WANRXP
WANRXP
WANRXP
RESETN
RESETN
RESETN
RESETN
RESETN
EROEN/
EROEN/
EROEN/
EROEN/
EROEN/
CPUCLK
CPUCLK
CPUCLK
CPUCLK
CPUCLK
URTSN/
URTSN/
URTSN/
URTSN/
URTSN/
WRSTO
WRSTO
WRSTO
WRSTO
WRSTO
XCLK1/
XCLK1/
XCLK1/
XCLK1/
XCLK1/
TRSTN
TRSTN
TRSTN
TRSTN
TRSTN
XCLK2
XCLK2
XCLK2
XCLK2
XCLK2
Name
Name
Name
Name
Name
Name
Name
Name
Name
TMS
TMS
TMS
TMS
TMS
TDO
TDO
TDO
TDO
TDO
TCK
TCK
TCK
TCK
TCK
TDI
TDI
TDI
TDI
TDI
I/O Type
I/O Type
I/O Type
I/O Type
I/O Type
I/O Type
I/O Type
I/O Type
I/O Type
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O/I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
(1)
(1)
(1)
Description
Description
External Clock In. This signal is used as the source clock for the transmit clock of the
External Clock In. This signal is used as the source clock for the transmit clock of the
External Clock In. This signal is used as the source clock for the transmit clock of the
External Clock In. This signal is used as the source clock for the transmit clock of the
External Clock In. This signal is used as the source clock for the transmit clock of the
internal MAC and PHY. The clock frequency is 25MHz ±50ppm. The XCLK1
internal MAC and PHY. The clock frequency is 25MHz ±50ppm. The XCLK1
internal MAC and PHY. The clock frequency is 25MHz ±50ppm. The XCLK1
internal MAC and PHY. The clock frequency is 25MHz ±50ppm. The XCLK1
internal MAC and PHY. The clock frequency is 25MHz ±50ppm. The XCLK1
signal is also used as the reference clock signal for the internal PLL to generate the
signal is also used as the reference clock signal for the internal PLL to generate the
signal is also used as the reference clock signal for the internal PLL to generate the
signal is also used as the reference clock signal for the internal PLL to generate the
signal is also used as the reference clock signal for the internal PLL to generate the
125MHz internal system clock.
125MHz internal system clock.
125MHz internal system clock.
125MHz internal system clock.
125MHz internal system clock.
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
This is unused for a normal clock input.
This is unused for a normal clock input.
This is unused for a normal clock input.
This is unused for a normal clock input.
This is unused for a normal clock input.
Normal Mode: UART request to send. Active low output.
Normal Mode: UART request to send. Active low output.
Normal Mode: UART request to send. Active low output.
Normal Mode: UART request to send. Active low output.
Normal Mode: UART request to send. Active low output.
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
mode), the internal PLL clock output is used as the CPU clock source.
mode), the internal PLL clock output is used as the CPU clock source.
mode), the internal PLL clock output is used as the CPU clock source.
mode), the internal PLL clock output is used as the CPU clock source.
mode), the internal PLL clock output is used as the CPU clock source.
CPUCLKSEL=1 (factory reserved test signal).
CPUCLKSEL=1 (factory reserved test signal).
CPUCLKSEL=1 (factory reserved test signal).
CPUCLKSEL=1 (factory reserved test signal).
CPUCLKSEL=1 (factory reserved test signal).
KS8695PX chip reset. Active low input asserted for at least 256 system clock (40ns)
KS8695PX chip reset. Active low input asserted for at least 256 system clock (40ns)
KS8695PX chip reset. Active low input asserted for at least 256 system clock (40ns)
KS8695PX chip reset. Active low input asserted for at least 256 system clock (40ns)
KS8695PX chip reset. Active low input asserted for at least 256 system clock (40ns)
cycles to reset the KS8695PX. When in the reset state, all the output pins are
cycles to reset the KS8695PX. When in the reset state, all the output pins are
cycles to reset the KS8695PX. When in the reset state, all the output pins are
cycles to reset the KS8695PX. When in the reset state, all the output pins are
cycles to reset the KS8695PX. When in the reset state, all the output pins are
tri-stated and all open drain signals are fl oating.
tri-stated and all open drain signals are fl oating.
tri-stated and all open drain signals are fl oating.
tri-stated and all open drain signals are fl oating.
tri-stated and all open drain signals are fl oating.
Watchdog timer reset output. This signal is asserted for at least 200ms if
Watchdog timer reset output. This signal is asserted for at least 200ms if
Watchdog timer reset output. This signal is asserted for at least 200ms if
Watchdog timer reset output. This signal is asserted for at least 200ms if
Watchdog timer reset output. This signal is asserted for at least 200ms if
RESETN is asserted or when the internal watchdog timer expires.
RESETN is asserted or when the internal watchdog timer expires.
RESETN is asserted or when the internal watchdog timer expires.
RESETN is asserted or when the internal watchdog timer expires.
RESETN is asserted or when the internal watchdog timer expires.
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low. When
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low. When
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low. When
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low. When
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low. When
asserted, this signal controls the output enable port of the specifi ed device.
asserted, this signal controls the output enable port of the specifi ed device.
asserted, this signal controls the output enable port of the specifi ed device.
asserted, this signal controls the output enable port of the specifi ed device.
asserted, this signal controls the output enable port of the specifi ed device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
WRSTPLS=1, Active low. No default.
WRSTPLS=1, Active low. No default.
WRSTPLS=1, Active low. No default.
WRSTPLS=1, Active low. No default.
WRSTPLS=1, Active low. No default.
Description
Description
JTAG test clock.
JTAG test clock.
JTAG test clock.
JTAG test clock.
JTAG test clock.
JTAG test mode select.
JTAG test mode select.
JTAG test mode select.
JTAG test mode select.
JTAG test mode select.
JTAG test data in.
JTAG test data in.
JTAG test data in.
JTAG test data in.
JTAG test data in.
JTAG test data out.
JTAG test data out.
JTAG test data out.
JTAG test data out.
JTAG test data out.
JTAG test reset. Active low.
JTAG test reset. Active low.
JTAG test reset. Active low.
JTAG test reset. Active low.
JTAG test reset. Active low.
Description
Description
WAN PHY transmit signal + (differential).
WAN PHY transmit signal + (differential).
WAN PHY transmit signal + (differential).
WAN PHY transmit signal + (differential).
WAN PHY transmit signal + (differential).
WAN PHY transmit signal – (differential).
WAN PHY transmit signal – (differential).
WAN PHY transmit signal – (differential).
WAN PHY transmit signal – (differential).
WAN PHY transmit signal – (differential).
WAN PHY receive signal + (differential).
WAN PHY receive signal + (differential).
WAN PHY receive signal + (differential).
WAN PHY receive signal + (differential).
WAN PHY receive signal + (differential).
WAN PHY receive signal – (differential).
WAN PHY receive signal – (differential).
WAN PHY receive signal – (differential).
WAN PHY receive signal – (differential).
WAN PHY receive signal – (differential).
WAN fi ber signal detect. Signal detect input when the WAN port is operated in
WAN fi ber signal detect. Signal detect input when the WAN port is operated in
WAN fi ber signal detect. Signal detect input when the WAN port is operated in
WAN fi ber signal detect. Signal detect input when the WAN port is operated in
WAN fi ber signal detect. Signal detect input when the WAN port is operated in
100BASE-FX 100Mb fi ber mode. See Application Note 10.
100BASE-FX 100Mb fi ber mode. See Application Note 10.
100BASE-FX 100Mb fi ber mode. See Application Note 10.
100BASE-FX 100Mb fi ber mode. See Application Note 10.
100BASE-FX 100Mb fi ber mode. See Application Note 10.
23
September 2005
Micrel