MAX17082GTL+ Maxim Integrated Products, MAX17082GTL+ Datasheet - Page 16

• Manufacturer Part Number: MAX17082GTL+
• Description: IC CTLR PWM DUAL IMVP-6.5 40TQFN
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX17082GTL+

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 4.5 ~ 5.5 V
• Number Of Outputs: 1
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Details

Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
16
PIN
13
14
15
16
17
18
19
______________________________________________________________________________________
DPRSLPVR
PWRGD
NAME
V3P3
TON
Shutdown Control Input. This input cannot withstand the battery voltage. Connect to V
operation. Connect to ground to put the IC into its 1μA max shutdown state. During startup, the output
voltage is ramped up to the boot voltage slowly at a slew rate that is 1/8 the slew rate set by the TIME
resistor. During the transition from normal operation to shutdown, the output voltage is ramped down at
the same slow slew rate. Forcing
undervoltage-protection circuits, clears the fault latch, disables transient phase overlap, and disables
the BST_ charging switches. Do not connect
Pulse-Skipping Control Input. This 1.0V logic input signal indicates power usage and sets the operating
mode of MAX17021/MAX17082/MAX17482. When DPRSLPVR is forced high, the controller immediately
enters the automatic pulse-skipping mode. The controller returns to forced-PWM mode when DPRSLPVR is
forced low and the output is in regulation. The PWRGD upper threshold is blanked during any downward
output-voltage transition that occurs when the controller is in pulse-skipping mode, and stays blanked until
the transition-related PWRGD blanking period is complete and the output reaches regulation. The output
overvoltage fault threshold is changed from a tracking [VID + 300mV] threshold to a fixed-default
transitional OVP threshold during the period for which the PWRGD upper threshold is blanked.
The MAX17082 is in two-phase pulse-skipping mode during startup and while in boot mode, but is in
forced-PWM mode during the transition from boot mode to VID mode plus 20μs, and during soft-
shutdown, irrespective of the DRPSLPVR logic level.
DPRSLPVR and
in the following truth table:
Power-State Indicator Input. DPRSLPVR and
of active phases as shown in the truth table included under the
Switching Frequency Setting Input. An external resistor between the input power source and TON sets
the switching period (T
TON becomes high impedance in shutdown to reduce the input quiescent current. If the TON current is
less than 10μA, the MAX17021/MAX17082/MAX17482 disable the controller, set the TON open fault
latch, and pull DL_ and DH_ low.
3.3V CLKEN Input Supply. V3P3 input supplies the
the system’s standard 3.3V supply voltage before
Clock Enable Push-Pull Logic Output. This inverted logic output indicates when the output voltage
sensed at FB is in regulation. During soft-start, shutdown, and when the FB is out of regulation, the
MAX17021/MAX17082/MAX17482 pull
Timing Diagram (Figure 10). When in pulse-skipping mode (DPRSLPVR high), the upper
is disabled.
Open-Drain Power-Good Output. After output-voltage transitions, except during power-up and power-
down; if FB is in regulation then PWRGD is high impedance.
During startup, PWRGD is held low and continues to be low while the part is in boot mode and until
5ms (typ) after
PWRGD is forced low in shutdown.
PWRGD is forced high impedance whenever the slew-rate controller is active (output-voltage transitions).
When in pulse-skipping mode (DPRSLPVR high), the upper PWRGD threshold comparator is blanked
during downward transitions.
A pullup resistor on PWRGD causes additional finite shutdown current.
DPRSLPVR
low. Except during the power-up sequence,
1
1
0
0
together determine the operating mode and the number of active phases as shown
PSI
0
1
0
1
goes low.
SW
= 1/f
SW
MODE AND PHASES
Very low current (one-phase pulse skipping)
Low current (approx 3A) (one-phase pulse skipping)
Intermediate power potential (one-phase PWM)
Max power potential ( two- or one-phase PWM as configured at CSP2)
) per phase according to the following equation:
T
SW
to 11V~13V disables both overvoltage-protection and
= 16.3pF x (R
up to V3P3. During VID transitions, the controller forces
FUNCTION
together determine the operating mode and the number
to > 13V.
TON
Pin Description (continued)
is pulled high for proper IMVP-6.5 operation.
is the inverse of PWRGD. See the Startup
+ 6.5k )
CMOS push-pull logic output. Connect to
pin description above.
CC
for normal
threshold