MAX17082GTL+ Maxim Integrated Products, MAX17082GTL+ Datasheet - Page 15

• Manufacturer Part Number: MAX17082GTL+
• Description: IC CTLR PWM DUAL IMVP-6.5 40TQFN
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX17082GTL+

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 4.5 ~ 5.5 V
• Number Of Outputs: 1
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Details

PIN
10
11
12
4
5
6
7
8
9
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
NAME
FBAC
GNDS
CSN2
CSP2
TIME
ILIM
V
CCI
FB
CC
______________________________________________________________________________________
Dual-Phase, Quick-PWM Controllers for
Valley Current-Limit Adjustment Input. The valley current-limit threshold voltage at CSP_ to CSN_
equals precisely 1/10 of the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV
current-sense range). The negative current-limit threshold is nominally -125% of the corresponding
valley current-limit threshold. Connect ILIM directly to V
setting of 22.5mV (typ) nominal.
Slew-Rate Adjustment Pin. TIME regulates to 2.0V and the load current determines the slew rate of the
internal error-amplifier target. The sum of the resistance between TIME and GND (R
nominal slew-rate:
The guaranteed R
transitions and to the transition from boot mode to VID. If the VID DAC inputs are clocked, the slew rate for
all other VID transitions is set by the rate at which they are clocked, up to a maximum slew rate equal to
the nominal slew rate defined above.
The startup and shutdown slew rates are always 1/8 of nominal slew rate in order to minimize surge
currents.
MAX17021: If both DPRSLPVR and
MAX17082/MAX17482: If
Controller Analog Bias Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1μF minimum.
Current-Balance Compensation. Connect a 470pF capacitor between CCI and the positive side of the
feedback remote sense. CCI is internally forced low in shutdown.
Remote Feedback-Sense Input. Normally shorted to FBAC and connected to the VCC_SENSE pin of the
CPU socket through the load-line gain resistor (see the FBAC pin description). FB internally connects
to the error amplifier and integrator.
Voltage-Positioning Transconductance Amplifier Output. Connect a resistor R
positive side of the feedback remote sense to set the DC steady-state droop based on the voltage-
positioning gain requirement:
where R
value of the current-sense resistors that are used to provide the (CSP_, CSN_) current-sense voltages. If
lossless sensing is used, R
includes an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope.
FBAC is high impedance in shutdown.
Remote Ground-Sense Input. Normally connected to the VSS_SENSE pin of the CPU socket. GNDS
internally connects to a transconductance amplifier that fine tunes the output voltage—compensating
for voltage drops from the regulator ground to the load ground.
Negative Current-Sense Input for Phase 2. Connect CSN2 to the negative terminal of the inductor
current-sensing resistor or directly to the negative terminal of the inductor if the lossless DCR sensing
method is used (see Figure 4).
Positive Current-Sense Input for Phase 2. Connect CSP2 to the positive terminal of the inductor current-
sensing resistor or directly to the positive terminal of the filtering capacitor used when the lossless
DCR sensing method is used (see Figure 4). Short CSP2 to V
DROOP
is the desired voltage-positioning slope and G
TIME
range is between 35.7k and 178k . This “nominal” slew rate applies to VID
SENSE
is low, then the slew rate is reduced to 1/2 of nominal.
SLEW RATE = (12.5mV/μs) x (71.5k /RTIME)
R
FB
= R
= R
L
DROOP
. In this case, consider making R
are pulled high, then the slew rate is reduced to 1/4 of nominal.
FUNCTION
/(R
SENSE
Pin Description (continued)
CC
x G
to set the default current-limit threshold
m(FBAC)
CC
m(FBAC)
for dedicated one-phase operation.
)
= 600μS (typ). R
FB
a resistor network that
FB
TIME
between FBAC and the
) determines the
SENSE
is the
15