LT1950EGN Linear Technology, LT1950EGN Datasheet - Page 14

• Manufacturer Part Number: LT1950EGN
• Description: IC CTLR PWM SGL SWITCH 16-SSOP
• Manufacturer: Linear Technology

Specifications of LT1950EGN

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 560kHz
• Duty Cycle: 97%
• Voltage - Supply: 3 V ~ 25 V
• Buck: No
• Boost: Yes
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-SSOP
• Frequency-max: 560kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LT1950
APPLICATIO S I FOR ATIO
Programming Leading Edge Blank Time
For PWM controllers driving external MOSFETs, noise can
be generated during GATE rise time due to various para-
sitic effects. This noise can disturb the input to the current
sense comparator (I
of the external MOSFET. The LT1950 provides program-
mable leading edge blanking of the current sense com-
parator to avoid this effect.
Blanking is provided in 2 phases: The first phase is during
GATE rise time. GATE rise times vary depending on
MOSFET type. For this reason the LT1950 automatically
blanks the current comparator output until the “leading
edge” of the GATE is detected. This occurs when the GATE
voltage has risen within 0.5V of the output driver supply
(V
phase of blanking starts immediately after “leading edge”
has been detected. This phase is programmable using a
resistor (R
values for this portion of the blanking period are 110ns at
R
blanking vs R
mated as:
14
BLANK
IN2
BLANKING EXTENDED
) or has reached its clamp level of 13V. The second
= 0Ω up to 290ns at R
BLANK
BLANK
(
) from the BLANK pin to ground. Typical
U
. Blanking duration can be approxi-
SENSE
) and cause premature turn-off
U
)
BLANK
=
110
GATE
BLANKING
= 75k. Figure 8 shows
W
+
⎛
⎜
⎝
(AUTOMATIC)
60
BLANKING
LEADING
0
EDGE
•
R
Figure 8. Blanking Timing Diagram
Xns
BLANK
25
R
BLANK
U
(DEFAULT)
EXTENDED
BLANKING
k
= 0Ω
⎞
⎟
⎠
(X + 110)ns
ns
0Ω < R
(PROGRAMMABLE)
EXTENDED
BLANKING
Programming Volt-Second Clamp
The V
cycle clamp for sophisticated control of the simplest
forward converter topology (single primary-side switch).
This adaptive maximum duty cycle clamp allows the use of
the smallest transformers, MOSFETs and output rectifiers
by addressing the biggest concern in single switch for-
ward converter topologies - transformer reset. The sec-
tion “Application Circuits-Forward Converter Applications”
covers transformer reset requirements and highlights the
advantages of the LT1950 adaptive maximum duty cycle
clamp. The programmable maximum duty cycle clamp is
controlled by the voltage on the V
V
duty cycle decreases. By deriving V
the system input supply, a volt-second clamp is realized.
Maximum GATE output duty cycle follows a 1/X relation-
ship given by (105/V
V
istics section). For example, if the minimum input supply
for a forward converter application is 36V, the V
be programmed with a maximum duty cycle of 75% at
1.4V. A movement of input voltage to 72V will lift the V
pin to 2.8V, resulting in a maximum duty cycle of 37.5%.
As the section on Forward Converter Applications will
show, transformer reset requirements are met with the
BLANK
SEC
SEC
[X + 110 + (60 • R
< = 75k
Voltage graph in the Typical Performance Character-
SEC
pin increases within a specified range, maximum
pin is used to provide an adaptive maximum duty
CURRENT
SENSE
DELAY
BLANK
60ns
/25k)]ns
SEC
1950 F04
)%. (see Maximum Duty Cycle vs
SEC
pin. As voltage on the
SEC
pin voltage from
SEC
pin can
1950fa
SEC