ISL62383HRTZ Intersil, ISL62383HRTZ Datasheet - Page 15

• Manufacturer Part Number: ISL62383HRTZ
• Description: IC PWR SUPPLY CONTROLLER 28TQFN
• Manufacturer: Intersil

Specifications of ISL62383HRTZ

• Applications: Power Supply Controller
• Voltage - Supply: 5.5 V ~ 25 V
• Current - Supply: 150µA
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. It is an undefined impedance if
V
falling threshold. When a fault is detected, the ISL62381,
ISL62382 and ISL62383 will turn on the open-drain NMOS,
which will pull PGOOD low with a nominal impedance of 63Ω
or 95Ω. This will flag the system that one of the output
voltages is out of regulation.
Separate enable pins allow for full soft-start sequencing.
Because low shutdown quiescent current is necessary to
prolong battery life in notebook applications, the LDO5 5V
LDO is held off until any of the three enable signals (EN1,
EN2 or LDO3EN) is pulled high. Soft-start of all outputs will
only start until after LDO5 is above the 4.2V POR threshold.
In addition to user-programmable sequencing, the
ISL62381, ISL62382 and ISL62383 include a
pre-programmed sequential SMPS soft-start feature. Table 1
shows the SMPS enable truth table.
MOSFET Gate-Drive Outputs LGATE and UGATE
The ISL62381, ISL62382 and ISL62383 have internal
gate-drivers for the high-side and low-side N-Channel
MOSFETs. The low-side gate-drivers are optimized for low
duty-cycle applications where the low-side MOSFET
conduction losses are dominant, requiring a low r
MOSFET. The LGATE pull-down resistance is small in order
IN
Float
Float
Float
EN1
FIGURE 24. SOFT-START SEQUENCE FOR ONE SMPS
is not above the rising POR threshold or below the POR
0
0
0
1
1
1
TABLE 1. SMPS ENABLE SEQUENCE LOGIC
Float
Float
Float
EN2
0
0
1
0
1
1
PGOOD Delay
t
SOFTSTART
1.5ms
SMPS1 enables after SMPS2 is in regulation
SMPS2 enables after SMPS1 is in regulation
Both SMPS outputs OFF simultaneously
Both SMPS outputs OFF simultaneously
Both SMPS outputs OFF simultaneously
Both SMPS outputs OFF simultaneously
2.75ms
Both SMPS outputs ON simultaneously
15
SMPS1 OFF, SMPS2 ON
SMPS1 ON, SMPS2 OFF
START-UP SEQUENCE
VOUT
EN
FB
PGOOD
VCC and LDO5
ISL62381, ISL62382, ISL62383
DS(ON)
to clamp the gate of the MOSFET below the V
turnoff. The current transient through the gate at turn-off can
be considerable because the gate charge of a low r
MOSFET can be large. Adaptive shoot-through protection
prevents a gate-driver output from turning on until the
opposite gate-driver output has fallen below approximately
1V. The dead-time shown in Figure 25 is extended by the
additional period that the falling gate voltage stays above the
1V threshold. The typical dead-time is 21ns. The high-side
gate-driver output voltage is measured across the UGATE
and PHASE pins while the low-side gate-driver output
voltage is measured across the LGATE and PGND pins. The
power for the LGATE gate-driver is sourced directly from the
LDO5 pin. The power for the UGATE gate-driver is sourced
from a “boot” capacitor connected across the BOOT and
PHASE pins. The boot capacitor is charged from the 5V
LDO5 supply through a “boot diode” each time the low-side
MOSFET turns on, pulling the PHASE pin low. The
ISL62381, ISL62382 and ISL62383 have integrated boot
diodes connected from the LDO5 pins to BOOT pins.
Diode Emulation
FCCM is a logic input that controls the power state of the
ISL62381, ISL62382 and ISL62383. If forced high, the
ISL62381, ISL62382 and ISL62383 will operate in forced
continuous-conduction-mode (CCM) over the entire load
range. This will produce the best transient response to all
load conditions, but will have increased light-load power
loss. If FCCM is forced low, the ISL62381, ISL62382 and
ISL62383 will automatically operate in diode-emulation-
mode (DEM) at light load to optimize efficiency in the entire
load range. The transition is automatically achieved by
detecting the load current and turning off LGATE when the
inductor current reaches 0A.
Positive-going inductor current flows from either the source
of the high-side MOSFET, or the drain of the low-side
MOSFET. Negative-going inductor current flows into the
drain of the low-side MOSFET. When the low-side MOSFET
UGATE
LGATE
FIGURE 25. LGATE AND UGATE DEAD-TIME
t
LGFUGR
50%
50%
t
UGFLGR
GS(th)
August 7, 2008
DS(ON)
at
FN6665.4