ISL62383HRTZ Intersil, ISL62383HRTZ Datasheet - Page 14

• Manufacturer Part Number: ISL62383HRTZ
• Description: IC PWR SUPPLY CONTROLLER 28TQFN
• Manufacturer: Intersil

Specifications of ISL62383HRTZ

• Applications: Power Supply Controller
• Voltage - Supply: 5.5 V ~ 25 V
• Current - Supply: 150µA
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

Theory of Operation
Four Output Controller
The ISL62381 and ISL62382 generate four regulated output
voltages, including two PWM controllers and two LDOs. The
two PWM channels are identical and almost entirely
independent, with the exception of sharing the GND pin.
Unless otherwise stated, only one individual channel is
discussed, and the conclusion applies to both channels.
PWM Modulator
The ISL62381, ISL62382 and ISL62383 modulator features
Intersil’s R
control and variable frequency hysteretic control. Intersil’s
R
frequency and PWM duty cycle in response to input voltage
and output load transients. The R
AC signal V
output inductor ripple current. The duty-cycle of V
result of charge and discharge current through a ripple
capacitor C
transconductance amplifier g
VO pin voltages. The positive slope of V
Equation 1:
The negative slope of V
Where g
A window voltage V
amplifier output voltage V
which the ripple voltage V
V
pins. The V
comparator in which V
and V
shows PWM pulses being generated as V
V
V
RIPPLE CAPACITOR VOLTAGE V
RPOS
3
W
RNEG
FIGURE 23. MODULATOR WAVEFORMS DURING LOAD
technology can simultaneously affect the PWM switching
is set by a resistor connected across the FSET and GND
COMP
=
=
m
g
g
3
is the gain of the transconductance amplifier.
m
R
R,
m
R
technology, a hybrid of fixed frequency PWM
+ V
. The current through C
⋅
, which is an analog representation of the
⋅
TRANSIENT
(
V
V
V
COMP,
OUT
W
IN
is the higher threshold voltage. Figure 23
–
W
V
⁄
C
OUT
is referenced with respect to the error
COMP
and V
R
R
COMP
R
) C
can be written as Equation 2:
⁄
is compared. The amplitude of
W
14
m
R
is the lower threshold voltage
R
ERROR AMPLIFIER
VOLTAGE V
signals feed into a window
that measures the VIN and
, creating an envelope into
3
modulator synthesizes an
WINDOW VOLTAGE V
R
is provided by a
(WRT V
R
COMP
R
can be written as
PWM
ISL62381, ISL62382, ISL62383
traverses the
COMP
R
)
is the
(EQ. 2)
(EQ. 1)
W
V
frequency is proportional to the slew rates of the positive and
negative slopes of V
voltage between V
to calculate the window size based on output voltage and
frequency set resistor R
V
Programming the PWM Switching Frequency
The ISL62381, ISL62382, ISL62383 family does not use a
clock signal to produce PWMs. The PWM switching
frequency F
connected from the FSET pin to the GND pin. The
approximate PWM switching frequency can be expressed as
written inEquation 4:
F
For a desired F
R
where C
FSET pin voltage, a ceramic capacitor such as 10nF is
necessary to parallel with R
It is recommended that whenever the control loop
compensation network is modified, F
for the correct frequency and if necessary, adjust R
Power-On Reset
The ISL62381, ISL62382 and ISL62383 are disabled until
the voltage at the VIN pin has increased above the rising
power-on reset (POR) threshold voltage. The controller will
be disabled when the voltage at the VIN pin decreases
below the falling POR threshold.
In addition to VIN POR, the LDO5 pin is also monitored. If its
voltage falls below 4.2V, the SMPS outputs will be shut
down. This ensures that there is sufficient BOOT voltage to
enhance the upper MOSFET.
EN, Soft-Start and PGOOD
The ISL62381, ISL62382 and ISL62383 use a digital
soft-start circuit to ramp the output voltage of each SMPS to
the programmed regulation setpoint at a predictable slew
rate. The slew rate of the soft-start sequence has been
selected to limit the in-rush current through the output
capacitors as they charge to the desired regulation voltage.
When the EN pins are pulled above their rising thresholds, the
PGOOD Soft-Start Delay, t
begins to rise. The FB pin ramps to 0.6V in approximately
1.5ms and the PGOOD pin goes to high impedance
approximately 1.25ms after the FB pin voltage reaches 0.6V.
SW
COMP
W
W
=
=
=
g
------------------------------------
10 C
m
-------------------------------- -
10 C
and V
R
⋅
⋅
⋅
V
= 17pF with ±20% error range. To smooth the
R
OUT
SW
1
1
R
⋅
COMP
F
⋅
SW
R
SW
is programmed by the resistor R
⋅
W
(
1 D
, the R
W
–
R;
+ V
and V
) R
it is inversely proportional to the
W
⋅
W
W
.
SS
W
thresholds. The PWM switching
COMP.
W.
can be selected by Equation 5.
, starts and the output voltage
Equation 3 illustrates how
SW
should be checked
W
August 7, 2008
that is
W
.
FN6665.4
(EQ. 3)
(EQ. 4)
(EQ. 5)