AMIS30542C5421RG ON Semiconductor, AMIS30542C5421RG Datasheet - Page 18

IC MOTOR DVR MICRO STEP 32QFP

AMIS30542C5421RG

Manufacturer Part Number
AMIS30542C5421RG
Description
IC MOTOR DVR MICRO STEP 32QFP
Manufacturer
ON Semiconductor
Type
Micro Stepping Motor Driverr
Datasheet

Specifications of AMIS30542C5421RG

Applications
Stepper Motor Driver, 2 Phase
Number Of Outputs
1
Current - Output
2.2A
Voltage - Supply
6 V ~ 30 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
32-VSQFP
Product
Stepper Motor Controllers / Drivers
Operating Supply Voltage
6 V to 30 V
Supply Current
8 mA
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Load
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AMIS30542C5421RG
Manufacturer:
ON Semiconductor
Quantity:
1 500
Part Number:
AMIS30542C5421RG
Manufacturer:
ON Semiconductor
Quantity:
10 000
Warning, Error Detection and Diagnostics
Feedback
Thermal Warning and Shutdown
warning bit <TW> is set (Table 16 SPI Status registers
Address SR0). If junction temperature increases above
thermal shutdown level, then the circuit goes in “Thermal
Shutdown” mode (<TSD>) and all driver transistors are
disabled (high impedance) (see Table 16 SPI Status registers
Address SR2). The conditions to reset flag <TSD> is to be
at a temperature lower than T
by reading it using any SPI read command.
Overcurrent Detection
current in each activated output stage. If the load current
exceeds the over−current detection threshold, then the
overcurrent flag is set and the drivers are switched off to
reduce the power dissipation and to protect the integrated
circuit. Each driver transistor has an individual detection bit
in (see Table 16 SPI Status registers Address SR1 and SR2:
<OVCXij> and <OVCYij>). Error condition is latched
and the microcontroller needs to clean the status bits to
reactivate the drivers.
Note: Successive reading the SPI StatusRegisters 1 and 2 in
case of a short circuit condition, may lead to damage to the
drivers.
When junction temperature rises above T
The overcurrent detection circuit monitors the load
SLA−pin
PWMsh
Icoil=0
SLAT
V
COIL
PWMsh
V
Icoil=0
SLAT = 1 => SLA−pin is “transparent” during
V
Crossing. SLA−pin is updated “real−time”.
COIL
BEMF
tw
sampling @ Coil Current Zero
div2
div4
and to clear the <TSD> flag
Ssh
Figure 15. Timing Diagram of SLA−Pin
TW
, the thermal
Csh
http://onsemi.com
Sh
last sample
is retained
18
Ch
SLAT = 0 => SLA−pin is not “transparent” during
V
SLA−pin is updated when leaving current−less
state.
V
BEMF
BEMF
Open Coil/Current Not Reached Detection
duty cycle of the PWM regulator. If in a coil 100% duty cycle
is detected for longer than 200 ms then the related driver
transistors are disabled (high−impedance) and an
appropriate bit in the SPI status register is set (<OPENX> or
<OPENY>). (Table 16)
supply voltage is low, it can happen that the motor driver is
not able to deliver the requested current to the motor. Under
these conditions the PWM controller duty cycle will be
100% and after 200 ms the error pin and <OPENX>,
<OPENY> will flag this situation (motor current is kept
alive). This feature can be used to test if the operating
conditions (supply voltage, motor coil resistance) still allow
reaching the requested coil−current or else the coil current
should be reduced.
Charge Pump Failure
low R
voltages. If supply voltage is too low or external components
are not properly connected to guarantee R
drivers, then the bit <CPFAIL> is set (Table 16). Also after
POR the charge pump voltage will need some time to exceed
the required threshold. During that time <CPFAIL> will be
set to “1”.
SLAT
NOT(Icoil=0)
previous output is kept at SLA pin
Open coil detection is based on the observation of 100%
When the resistance of a motor coil is very large and the
The charge pump is an important circuit that guarantees
buf
sampling @ Coil Current Zero Crossing.
DS(on)
SLA− pin
for all drivers, especially for low supply
retain last sample
t
t
DS(on)
of the

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