TLE8102SG Infineon Technologies, TLE8102SG Datasheet - Page 9

• Manufacturer Part Number: TLE8102SG
• Description: IC SWITCH LOSIDE 2CH DSO-12
• Manufacturer: Infineon Technologies
• Type: Low Sider

Specifications of TLE8102SG

• Input Type: SPI
• Number Of Outputs: 2
• On-state Resistance: 180 mOhm
• Current - Peak Output: 6.5A
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: DSO-12
• Packages: PG-DSO-12
• Thermal Class: Heatslug down
• Id Nom: 2 x 2 A
• Pin Count: 12.0 Pins
• Channels: 2.0
• Comment: high current loads with sensing (e.g. O2)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output / Channel: -
• Other names: SP000308142; TLE8102SG; TLE8102SGTR

5
5.1
The TLE8102SG is supplied by power supply line V
device including the gate control of the power stages. A capacitor between pins V
The TLE8102SG can be programmed via SPI to enter sleep mode. In sleep mode, all outputs are turned off and
all diagnosis and biasing circuits are disabled. These actions reduce the quiescent current consumption from the
power supply. However, the SPI configuration registers (except for the channel on/off register) are not reset when
the TLE8102SG enters sleep mode. To exit sleep mode, a wake up command must be sent via SPI.
Electrical Characteristics: Power Supply
V
all voltages with respect to ground, positive current flowing into pin
Pos.
5.1.1
5.1.2
5.1.3
5.1.4
1) Not subject to production test, specified by design.
5.2
There are two input pins available on the TLE8102SG to control the output stages.
Each input signal controls the output stages of its assigned channel. For example, IN1 controls OUT1 and IN2
controls OUT2. Please refer to
pull-down current source. A comparator with hysteresis determines the state of the signal on INn. The zener diode
protects the input circuit against ESD pulses.
The BOL bit can be set via SPI. This bit determines if the output is exclusively controlled by the INn signals,
exclusively controlled by the corresponding data bits CHn
inputs. The default setting of the BOL bits programs the outputs to be controlled exclusively by the INn signals.
The SLEn bit can be set via SPI. This bit sets the slew rate of its assigned channel by selecting either slew rate 1
or slew rate 2. The slew rate also changes the over load switch off delay time (only for current limit 2).
Figure 5
Data Sheet
DD
= 4.5 V to 5.5 V,
Parameter
Supply Voltage
Supply Current
Supply Current in Sleep Mode
Wake up Time (after sleep mode)
Electrical and Functional Description of Blocks
Power Supply
Parallel Inputs
Input Control and Boolean Operator
T
j
IN1
= -40 C to +150 C, (unless otherwise specified)
Figure 5
I
IN1
for details. The input pins are active high and each have an integrated
1)
Symbol
V
I
I
t
wake
VDD
VDD(sleep)
DD
CH1
DD
, used for the digital as well as the analog functions of the
IN
9
Min.
4.5
–
–
–
OR
SPI
IN
&
IN
BOL
Electrical and Functional Description of Blocks
or by a Boolean OR or AND operation of the two
Smart Dual Channel Powertrain Switch
Limit Values
Typ.
–
–
–
–
control
SLE1
gate
Max.
5.5
5
10
100
channel 1
channel 2
DD
Unit
V
mA
to GND is recommended.
A
s
Conditions
–
–
–
–
V1.4, 2008-05-08
TLE8102SG