NCP5104DR2G ON Semiconductor, NCP5104DR2G Datasheet

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NCP5104DR2G

Manufacturer Part Number
NCP5104DR2G
Description
IC DRIVER HALF BRIDGE HV 8-SOIC
Manufacturer
ON Semiconductor
Type
High Side/Low Sider
Datasheet

Specifications of NCP5104DR2G

Configuration
Half Bridge
Input Type
Non-Inverting
Delay Time
620ns
Current - Peak
250mA
Number Of Configurations
1
Number Of Outputs
2
High Side Voltage - Max (bootstrap)
600V
Voltage - Supply
10 V ~ 20 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Product
Half-Bridge Drivers
Rise Time
160 ns
Fall Time
75 ns
Propagation Delay Time
620 ns
Supply Voltage (max)
20 V
Supply Voltage (min)
- 0.3 V
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Bridge Type
Half Bridge
Minimum Operating Temperature
- 55 C
Number Of Drivers
2
Output Voltage
0.7 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
NCP5104DR2G
NCP5104DR2GOSTR

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NCP5104
High Voltage, Half Bridge
Driver
outputs for direct drive of 2 N−channel power MOSFETs or IGBTs
arranged in a half−bridge configuration. It uses the bootstrap
technique to insure a proper drive of the High−side power switch.
Features
Typical Applications
© Semiconductor Components Industries, LLC, 2010
March, 2010 − Rev. 3
The NCP5104 is a High Voltage Power gate Driver providing two
for Signal Propagation
High Voltage Range: up to 600 V
dV/dt Immunity ±50 V/nsec
Gate Drive Supply Range from 10 V to 20 V
High and Low Drive Outputs
Output Source / Sink Current Capability 250 mA / 500 mA
3.3 V and 5 V Input Logic Compatible
Up to V
Extended Allowable Negative Bridge Pin Voltage Swing to −10 V
Matched Propagation Delays between Both Channels
1 Input with Internal Fixed Dead Time (520 ns)
Under V
Pin to Pin Compatible with Industry Standards
These are Pb−Free Devices
Half−Bridge Power Converters
CC
CC
Swing on Input Pins
LockOut (UVLO) for Both Channels
1
†For information on tape and reel specifications,
NCP5104PG
NCP5104DR2G
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Device
NCP5104 = Specific Device Code
A
L or WL
Y or YY
W or WW = Work Week
G or G
CASE 751
CASE 626
ORDERING INFORMATION
D SUFFIX
P SUFFIX
SOIC−8
PDIP−8
1
GND
VCC
PINOUT INFORMATION
SD
http://onsemi.com
IN
1
8 Pin Package
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
(Pb−Free)
(Pb−Free)
Package
SOIC−8
PDIP−8
1
2
3
4
Publication Order Number:
8
7
6
5
DIAGRAMS
8
1
MARKING
2500 / Tape & Reel
VBOOT
DRV_HI
BRIDGE
DRV_LO
50 Units / Rail
NCP5104
ALYW
P5104
Shipping
G
YYWW
NCP5104/D
AWLG

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NCP5104DR2G Summary of contents

Page 1

... GND 8 Pin Package ORDERING INFORMATION Device Package NCP5104PG PDIP−8 (Pb−Free) NCP5104DR2G SOIC−8 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 MARKING DIAGRAMS 8 P5104 ALYW ...

Page 2

Vbulk C1 GND Vcc C3 1 GND Vcc 2 IN NCP1395 GND NCP5104 GND GND Figure 1. Typical Application Resonant Converter (LLC type) + Vbulk C1 GND Vcc C3 GND 1 Vcc SG3526 2 IN MC34025 ...

Page 3

PIN DESCRIPTION Pin Name Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á IN Á Á Á Á Á Á Á Á Á Á Á Á ...

Page 4

ELECTRICAL CHARACTERISTIC (V Rating OUTPUT SECTION Output high short circuit pulsed current V DRV Output low short circuit pulsed current V DRV Output resistor (Typical value @ 25°C) Source Output resistor (Typical value @ 25°C) Sink High level output voltage, ...

Page 5

IN SD DRV_HI DRV_LO Note: DRV_HI output is in phase with the input 50% IN ton DRV_HI toff 90% DRV_LO 10% Figure 4. Input/Output Timing Diagram 50% tr toff 90% 90% Dead time 10% tf Ton = Toff + DT ...

Page 6

IN DeadTime1 DRV_HI toff_LO 90% Matching Delay1=toff_HI−toff_LO DRV_LO Matching Delay 2=(toff_LO+DT1)−(tof f _HI+DT2) Figure 6. Matching Propagation Delay Definition 50% SD DRV_HI DRV_LO Figure 7. Shutdown Waveform Definition 50% toff_HI 90% 10% DeadTime2 50% tsd_en tsd_dis 90% 10% http://onsemi.com ...

Page 7

T Low Side ON 650 600 550 T High Side ON 500 450 400 VOLTAGE (V) CC Figure 8. Turn ON Propagation Delay vs. Supply Voltage ( 160 ...

Page 8

Low Side r 120 100 80 t High Side VOLTAGE (V) CC Figure 14. Turn ON Risetime vs. Supply Voltage ( BOOT 80 ...

Page 9

V , VOLTAGE (V) CC Figure 20. Low Level Input Voltage Threshold vs. Supply Voltage (V CC 2.5 2.0 1.5 1.0 0 ...

Page 10

V , VOLTAGE (V) CC Figure 26. Logic “1” Input Current vs. Supply Voltage ( BOOT 1.0 0.8 0.6 0.4 0 ...

Page 11

I 350 src 300 250 200 150 100 VOLTAGE (V) CC Figure 32. Output Source Current vs. Supply Voltage ( BOOT 600 I High Side sink 500 I ...

Page 12

V , VOLTAGE (V) BOOT Figure 38. V Supply Current vs. Bootstrap BOOT Supply Voltage ( 240 200 160 120 4.0 8.0 12 ...

Page 13

nF LOAD 5.0 R GATE 0 0 100 200 300 400 SWITCHING FREQUENCY (kHz) Figure 44. I Consumption vs. Switching CC1 Frequency with 15 nC Load on Each Driver @ ...

Page 14

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 15

... SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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