ADE7754ARRL Analog Devices Inc, ADE7754ARRL Datasheet - Page 4

• Manufacturer Part Number: ADE7754ARRL
• Description: IC ENERGY METERING 24-SOIC TR
• Manufacturer: Analog Devices Inc

Specifications of ADE7754ARRL

• Rohs Status: RoHS non-compliant
• Input Impedance: 370 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 7mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Meter Type: 3 Phase
• For Use With: EVAL-ADE7754EBZ - BOARD EVALAUTION FOR ADE7754

ADE7754
TIMING CHARACTERISTICS
Parameter
Write Timing
Read Timing
NOTES
1
2
3
4
5
Sample tested during initial release and after any redesign or process change
See timing diagrams below and Serial Interface section of this data sheet.
Minimum time between read command and data read for all registers except
Measured with the load circuit in Figure 1 and defined as the time required for
Derived from the measured time taken by the data outputs to change 0.5 V
that may affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.
wavmode register, which is t
the output to cross 0.8 V or 2.4 V.
when loaded with the circuit in Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF
capacitor. The time quoted in the timing characteristics is the true bus relin-
quish time of the part and is independent of the bus loading.
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
3
4
5
5
SCLK
DOUT
SCLK
DIN
CS
DIN
CS
t
t
Spec
50
50
50
10
5
400
50
100
4
50
30
100
10
100
10
1
1
9
1
0
= 500 ns min.
0
0
t
2
A5
A5
t
COMMAND BYTE
3
COMMAND BYTE
t
A4
A4
4
Unit
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
µs (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
1, 2
A3
A3
(AV
T
MIN
A2
A2
t
DD
5
to T
Figure 2. Serial Write Timing
Figure 3. Serial Read Timing
= DV
Test Conditions/Comments
CS Falling Edge to First SCLK Falling Edge
SCLK Logic High Pulsewidth
SCLK Logic Low Pulsewidth
Valid Data Setup Time before Falling Edge of SCLK
Data Hold Time after SCLK Falling Edge
Minimum Time between the End of Data Byte Transfers
Minimum Time between Byte Transfers during a Serial Write
CS Hold Time after SCLK Falling Edge
Minimum Time between Read Command (i.e., a Write to Communication
Register) and Data Read
Minimum Time between Data Byte Transfers during a Multibyte Read
Data Access Time after SCLK Rising Edge following a Write to the
Communications Register
Bus Relinquish Time after Falling Edge of SCLK
Bus Relinquish Time after Rising Edge of CS
A1
A1
MAX
DD
= –40 C to +85 C, unless otherwise noted.)
A0
A0
= 5 V
t
7
–4–
t
9
t
11
5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz XTAL,
DB7
MOST SIGNIFICANT BYTE
DB7
MOST SIGNIFICANT BYTE
Figure 1. Load Circuit for Timing Specifications
TO
OUTPUT
PIN
DB0
t
50pF
12
C
DB0
L
t
7
t
10
200 A
1.6mA
DB7
LEAST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
DB7
t
6
I
I
OL
OH
t
13
DB0
DB0
2.1V
t
8
REV. 0