ADE7758ARWZ Analog Devices Inc, ADE7758ARWZ Datasheet
ADE7758ARWZ
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ADE7758ARWZ Summary of contents
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FEATURES Highly accurate; supports IEC 60687, IEC 61036, IEC 61268, IEC 62053-21, IEC 62053-22, and IEC 62053-23 Compatible with 3-phase/3-wire, 3-phase/4-wire, and other 3-phase services Less than 0.1% active energy error over a dynamic range of 1000 ...
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ADE7758 TABLE OF CONTENTS Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications ..................................................................................... 5 Timing Characteristics ................................................................ 6 Timing Diagrams .............................................................................. 7 Absolute Maximum Ratings ............................................................ 8 ...
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REVISION HISTORY 10/08—Rev Rev. D Changes to Figure 1 ........................................................................... 1 Changes to Phase Sequence Detection Section and Figure Changes to Current RMS Calculation Section ............................ 28 Changes to Voltage Channel RMS Calculation Section and ...
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ADE7758 GENERAL DESCRIPTION (continued from Page 1) The ADE7758 has a waveform sample register that allows access to the ADC outputs. The part also incorporates a detection circuit for short duration low or high voltage variations. The voltage threshold levels ...
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SPECIFICATIONS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, T Table Parameter ACCURACY Active Energy Measurement Error (per Phase) Phase Error Between Channels PF ...
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ADE7758 1, 2 Parameter LOGIC OUTPUTS IRQ, DOUT, and CLKOUT Output High Voltage Output Low Voltage APCF and VARCF Output High Voltage Output Low Voltage POWER SUPPLY AVDD DVDD ...
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TIMING DIAGRAMS SCLK DIN COMMAND BYTE SCLK DIN DOUT COMMAND BYTE 200µ OUTPUT PIN C L 50pF 1.6mA I ...
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ADE7758 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter AVDD to AGND DVDD to DGND DVDD to AVDD Analog Input Voltage to AGND, IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP, VCP, VN Reference Input ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 APCF Active Power Calibration Frequency (APCF) Logic Output. It provides active power information. This output is used for operational and calibration purposes. The full-scale output ...
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ADE7758 Pin No. Mnemonic Description 17 VARCF Reactive Power Calibration Frequency Logic Output. It gives reactive power or apparent power information depending on the setting of the VACF bit of the WAVMODE register. This output is used for operational and ...
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TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7758 is defined by = Measuremen t Error Energy Registered by ADE7758 – True True Energy Phase Error Between Channels The high-pass filter (HPF) and digital integrator ...
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ADE7758 TYPICAL PERFORMANCE CHARACTERISTICS 0 0.4 0.3 0.2 0.1 +25°C 0 –40°C –0.1 –0.2 –0.3 +85°C –0.4 –0.5 0.01 0.1 1 PERCENT FULL-SCALE CURRENT (%) Figure 6. Active Energy Error as a Percentage of Reading (Gain = ...
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0.20 0.15 PHASE A 0.10 0.05 0 –0.05 PHASE B –0.10 –0.15 –0.20 –0.25 0.01 0.1 1 PERCENT FULL-SCALE CURRENT (%) Figure 12. APCF Error as a Percentage of Reading (Gain = +1) with Internal Reference ...
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ADE7758 0.10 0.08 0.06 5.25V 0.04 0.02 0 –0.02 –0.04 4.75V –0.06 –0.08 –0.10 0.01 0.1 1 PERCENT FULL-SCALE CURRENT (%) Figure 18. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Supply with Internal Reference and ...
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PERCENT FULL-SCALE CURRENT (%) Figure 24. Reactive Energy Error as a Percentage of Reading (Gain = +4) over Temperature with Internal Reference and Integrator On 0.5 0.4 ...
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ADE7758 1.5 1.0 –40 ° C 0.5 +25 ° –0.5 +85 ° C –1.0 –1.5 0.01 0.1 1 PERCENT FULL-SCALE CURRENT (%) Figure 30. Apparent Energy Error as a Percentage of Reading (Gain = +1) over Temperature with ...
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TEST CIRCUITS CURRENT TRANSFORMER I 1MΩ 220V 1kΩ CT TURN RATIO 1800:1 CHANNEL 2 GAIN = +1 CHANNEL 1 GAIN di/dt SENSOR I 1MΩ 220V 1kΩ CHANNEL 1 GAIN = +8 CHANNEL 2 GAIN = ...
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ADE7758 THEORY OF OPERATION ANTIALIASING FILTER This filter prevents aliasing, which is an artifact of all sampled systems. Input signals with frequency components higher than half the ADC sampling rate distort the sampled signal at a fre- quency below half ...
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Bit 7 of the gain register is used to enable the digital integrator in the current signal path. Setting this bit activates the digital integrator (see the DI/DT Current Sensor and Digital Integrator section). CURRENT CHANNEL ADC Figure 41 shows ...
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ADE7758 di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR The di/dt sensor detects changes in the magnetic field caused by the ac current. Figure 42 shows the principle of a di/dt current sensor. MAGNETIC FIELD CREATED BY CURRENT (DIRECTLY PROPORTIONAL TO CURRENT) ...
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Note that the integrator has a −20 dB/dec attenuation and approximately −90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. However, the di/dt ...
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ADE7758 VAP + VA PGA – ANALOG INPUT RANGE 0V VOLTAGE CHANNEL ADC Figure 49 shows the ADC and signal processing chain for the input VA in the voltage channel. The VB and VC channels have similar processing ...
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The sign of the register is extended in the upper 8 bits. The timing is the same as for the current channels, as seen in Figure 40. ZERO-CROSSING DETECTION The ADE7758 has zero-crossing detection circuits for each of the voltage ...
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ADE7758 The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7758 provides a means of digitally calibrating these small phase errors. The ADE7758 allows a small time delay or time advance to be introduced into ...
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IAP PGA1 IA IAN VAP PGA2 60Hz PERIOD MEASUREMENT The ADE7758 provides the period or frequency measurement of the line voltage. The period is measured on the phase specified by Bit 0 to Bit 1 of ...
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ADE7758 SAG LEVEL SET The contents of the single-byte SAG level register, SAGLVL[0:7], are compared to the absolute value of Bit 6 to Bit 13 from the voltage waveform samples. For example, the nominal maximum code of the voltage channel ...
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PHASE SEQUENCE DETECTION The ADE7758 has an on-chip phase sequence error detection interrupt. If the zero crossing of Phase A is not followed by Phase C but by Phase B, the SEQERR bit (Bit 19) in the STATUS register is ...
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ADE7758 TEMPERATURE MEASUREMENT The ADE7758 also includes an on-chip temperature sensor. A temperature measurement is made every 4/CLKIN seconds. The output from the temperature sensing circuit is connected to an ADC for digitizing. The resultant code is processed and placed ...
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Current RMS Offset Compensation The ADE7758 incorporates a current rms offset compensation register for each phase (AIRMSOS, BIRMSOS, and CIRMSOS). These are 12-bit signed registers that can be used to remove offsets in the current rms calculations. An offset can ...
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ADE7758 Voltage RMS Gain Adjust The ADC gain in each phase of the voltage channel can be adjusted for the rms calculation by using the voltage rms gain registers (AVRMSGAIN, BVRMSGAIN, and CVRMSGAIN). The gain of the voltage waveforms before ...
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Active Power Gain Calibration Note that the average active power result from the LPF output in each phase can be scaled by ±50% by writing to the phase’s watt gain register (AWG, BWG, or CWG). The watt gain registers are ...
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ADE7758 DIGITAL HPF INTEGRATOR I CURRENT SIGNAL–i(t) 0x2851EC 0x00 0xD7AE14 Φ V PHCAL[6:0] 0xCCCCD VOLTAGE SIGNAL–v(t) 0x2852 000x 0x00000 0xD7AE The ADE7758 achieves the integration of the active power signal by continuously accumulating the active power signal in the internal ...
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Integration Time Under Steady Load The discrete time sample period (T) for the accumulation register is 0.4 μs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the watt gain registers set to 0x000, the average word value from ...
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ADE7758 The maximum output frequency (APCFNUM = 0x00 and APCFDEN = 0x00) with full-scale ac signals on one phase is approximately 16 kHz. The ADE7758 incorporates two registers to set the frequency of APCF (APCFNUM[11:0] and APCFDEN[11:0]). These are unsigned ...
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Phase A, Phase B, and Phase C zero crossings are, respectively, included when counting the number of half-line cycles by setting ZXSEL[0:2] bits (Bit 3 to Bit 5) in the LCYCMODE register. Any combination of the zero crossings from all ...
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ADE7758 The frequency response of the LPF in the reactive power signal path is identical to that of the LPF2 used in the average active power calculation (see Figure 65). INSTANTANEOUS REACTIVE POWER SIGNAL q(t) = VRMS × IRMS × ...
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Reactive Energy Calculation Reactive energy is defined as the integral of reactive power ∫ Reactive Energy Similar to active power, the ADE7758 achieves the integration of the reactive power signal by continuously accumulating the ...
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ADE7758 Integration Time Under Steady Load The discrete time sample period (T) for the accumulation register is 0.4 μs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs, a 90° phase difference between the voltage and the current signal (the ...
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Line Cycle Reactive Energy Accumulation Mode The line cycle reactive energy accumulation mode is activated by setting the LVAR bit (Bit 1) in the LCYCMODE register. The total reactive energy accumulated over an integer number of zero crossings is written ...
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ADE7758 Apparent Energy Calculation Apparent energy is defined as the integral of apparent power. Apparent Energy = ∫ )dt Similar to active and reactive energy, the ADE7758 achieves the integration of the apparent power signal by continuously ...
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Table 14. Inputs to VA-Hr Accumulation Registers 1 CONSEL[1, 0] AVAHR 00 AVRMS × AIRMS 01 AVRMS × AIRMS 10 AVRMS × AIRMS 11 Reserved 1 AVRMS/BVRMS/CVRMS are the rms voltage waveform, and AIRMS/BIRMS/CIRMS are the rms values of the ...
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ADE7758 The interrupt request output IRQ stays low until the interrupt routine reads the reset status register (see the CALIBRATION A reference meter or an accurate source is required to calibrate the ADE7758 energy meter. When using a reference meter, ...
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YES ALL PHASES VAR OFFSET YES ALL PHASES NO WATT OFFSET CAL? SET UP PULSE OUTPUT FOR END CALIBRATE WATT OFFSET @ MIN Gain Calibration Using Pulse Output Gain calibration is ...
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ADE7758 SELECT VAR FOR VARCF OUTPUT ALL PHASES YES VAR GAIN CALIBRATED? END STEP 4 SET VARCFNUM/VARCFDEN TO CALCULATED VALUES Step 1: Enable the pulse output by setting Bit 2 of the OPMODE register (0x13) to Logic 0. This bit ...
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Step 4: Set APCFNUM (0x45) and APCFDEN (0x46) to the calculated value to perform a coarse adjustment on the imp/kWh ratio. For VAR/VA calibration, set VARCFNUM (0x47) and VARCFDEN (0x48) to the calculated value. The pulse output frequency with one ...
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ADE7758 . − = − AWG – 215 5 . 216 . 0 0244 % Phase Calibration Using Pulse Output The ADE7758 includes a phase calibration register on each phase to compensate for small phase ...
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YES END Step 1: Repeat Step 1 and Step 3 from the gain calibration to configure the ADE7758 pulse output. Step 2: Clear the xWATTOS and xVAROS registers. Step3: Disable the Phase B and Phase C contribution to the APCF ...
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ADE7758 = xVAROS ⎛ %VARCF × ⎜ ERROR – VARCF EXPECTED ⎝ 100 % VARCFDEN VARCFNUM where Q is defined in Equation 58 and Equation 59. For xWATTOS, CLKIN × × For ...
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Gain Calibration Using Line Accumulation Gain calibration is used for meter-to-meter gain adjustment, APCF or VARCF output rate calibration, and determining the Wh/LSB, VARh/LSB, and VAh/LSB constant. Step 0: Before performing the gain calibration, the APCFNUM/ APCFDEN (0x45/0x46) and VARCFNUM/ ...
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ADE7758 Step 5: Set the LENERGY bit, MASK[12] (0x18), to Logic 1 to enable the interrupt signaling the end of the line cycle accumulation. Step 6: Set the test system for TEST NOM (calibrate watt and VA ...
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To set APCFNUM (0x45) and APCFDEN (0x46) to the calculated value to perform a coarse adjustment on the imp/kW-hr ratio, use Equation 45 to Equation 47. 220 10 = × × APCF NOMINAL 500 130 × × ...
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ADE7758 where PHCAL_LSB_Weight is 1.2 μs if the %Error is negative or 2.4 μs if the %Error is positive (see the Phase Compensation section not known, the line period is available in the ADE7758’s frequency register, FREQ ...
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Power Offset Calibration Using Line Accumulation Power offset calibration should be used for outstanding performance over a wide dynamic range (1000:1). Calibration of the power offset is done at or close to the minimum current. The ADE7758 has power offset ...
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ADE7758 × 0 4000 = AccumTime 1 × 2 − × × 2085 × 0.161 4 = × AWATTOS 2 × 54.64 10 MHz Calibration of IRMS and VRMS Offset IRMSOS and VRMSOS are used to ...
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Step 1: Set configuration registers for zero crossings on all phases by writing the value 0x38 to the LCYCMODE register (0x17). This sets all of the ZXSEL bits to Logic 1. Step 2: Set the interrupt mask register for zero-crossing ...
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ADE7758 INTERRUPTS The ADE7758 interrupts are managed through the interrupt status register (STATUS[23:0], Address 0x19) and the interrupt mask register (MASK[23:0], Address 0x18). When an interrupt event occurs in the ADE7758, the corresponding flag in the interrupt status register is ...
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IRQ JUMP GLOBAL PROGRAM TO INTERRUPT SEQUENCE ISR MASK SCLK DIN 0 0 DOUT READ STATUS REGISTER COMMAND IRQ COMMUNICATIONS DIN REGISTER REGISTER NO. 1 DOUT OUT REGISTER NO. 2 OUT REGISTER NO. 3 OUT ...
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ADE7758 As explained earlier, the data write is initiated by a write to the communications register followed by the data. During a data write operation to the ADE7758, data is transferred to all on- chip registers one byte at a ...
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SERIAL READ OPERATION During a data read operation from the ADE7758, data is shifted out at the DOUT logic output on the rising edge of SCLK. As was the case with the data write operation, a data read must be ...
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ADE7758 REGISTERS COMMUNICATIONS REGISTER The communications register is an 8-bit, write-only register that controls the serial data transfer between the ADE7758 and the host processor. All data transfer operations must begin with a write to the communications register. Table 16. ...
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Address 1 [A6:A0] Name R/W Length 0x0E BVRMS R 24 0x0F CVRMS R 24 0x10 FREQ R 12 0x11 TEMP R 8 0x12 WFORM R 24 0x13 OPMODE R/W 8 0x14 MMODE R/W 8 0x15 WAVMODE R/W 8 0x16 COMPMODE ...
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ADE7758 Address 1 [A6:A0] Name R/W Length 0x22 IPEAK R 8 0x23 GAIN R/W 8 0x24 AVRMSGAIN R/W 12 0x25 BVRMSGAIN R/W 12 0x26 CVRMSGAIN R/W 12 0x27 AIGAIN R/W 12 0x28 BIGAIN R/W 12 0x29 CIGAIN R/W 12 0x2A ...
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Address 1 [A6:A0] Name R/W Length 0x45 APCFNUM R/W 16 0x46 APCFDEN R/W 12 0x47 VARCFNUM R/W 16 0x48 VARCFDEN R/W 12 0x49 to RESERVED − − 0x7D 0x7E CHKSUM R 8 0x7F VERSION This column specifies ...
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ADE7758 OPERATIONAL MODE REGISTER (0x13) The general configuration of the ADE7758 is defined by writing to the OPMODE register. Table 18 summarizes the functionality of each bit in the OPMODE register. Table 18. OPMODE Register Bit Bit Default Location Mnemonic ...
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WAVEFORM MODE REGISTER (0x15) The waveform sampling mode of the ADE7758 is defined by writing to the WAVMODE register. Table 20 summarizes the functionality of each bit in the WAVMODE register. Table 20. WAVMODE Register Bit Bit Default Location Mnemonic ...
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ADE7758 COMPUTATIONAL MODE REGISTER (0x16) The computational method of the ADE7758 is defined by writing to the COMPMODE register. Table 21 summarizes the functionality of each bit in the COMPMODE register. Table 21. COMPMODE Register Bit Bit Default Location Mnemonic ...
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LINE CYCLE ACCUMULATION MODE REGISTER (0x17) The functionalities involved the line-cycle accumulation mode in the ADE7758 are defined by writing to the LCYCMODE register. Table 22 summarizes the functionality of each bit in the LCYCMODE register. Table 22. LCYCMODE Register ...
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ADE7758 INTERRUPT MASK REGISTER (0x18) When an interrupt event occurs in the ADE7758, the IRQ logic output goes active low if the mask bit for this event is Logic 1 in the MASK register. The IRQ logic output is reset ...
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INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A) The interrupt status register is used to determine the source of an interrupt event. When an interrupt event occurs in the ADE7758, the corresponding flag in the interrupt status register is set. ...
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... COPLANARITY 0.10 ORDERING GUIDE Model Temperature Range ADE7758ARW −40° 85°C ADE7758ARWRL −40° 85°C ADE7758ARWZ 1 −40° 85°C 1 ADE7758ARWZRL −40° 85°C 1 EVAL-ADE7758EBZ RoHS Compliant Part. 15.60 (0.6142) 15.20 (0.5984 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193 ...
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NOTES Rev Page ADE7758 ...
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ADE7758 NOTES ©2004–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04443-0-10/08(D) Rev Page ...