CS5464-ISZ Cirrus Logic Inc, CS5464-ISZ Datasheet
CS5464-ISZ
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CS5464-ISZ Summary of contents
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... Power Supply Configurations GND VA VD+: +3 http://www.cirrus.com Description The CS5464 is a watt-hour meter on a chip. It measures line voltage and current and calcu- lates active, reactive, apparent power, energy, power factor, and RMS voltage and current. There are two separate inputs to measure line, ...
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... Low-Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 RMS Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8 Power and Energy Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9 Peak Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.10 Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 Analog Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.1 Voltage Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.2 Current1 and Current2 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.3 Power Fail Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2 CS5464 TABLE OF CONTENTS DS682F1 ...
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... Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.1 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.2 CPU Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.3 Interrupt Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.4 Energy Pulse Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.5 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. Setting Up the CS5464 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 CPU Clock Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 Interrupt Pin Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 Current Input Gain Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 ...
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... Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13. Ordering Information 14. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . 44 15. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 1. CS5464 Read and Write Timing Diagrams ................................................................. 12 Figure 2. Timing Diagram for E1 Figure 3. Signal Flow for V1, I1, P1, Q1 Measurements ............................................................ 14 Figure 4. Signal Flow for V2, I2, P2, Q2 Measurements ............................................................ 14 Figure 5 ...
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... The CS5464 includes a three-wire serial host interface to an external microcontroller or serial E Signals include serial data input (SDI), serial data output (SDO), serial clock (SCLK), and optionally, a chip select (CS), which allows the CS5464 to share the SDO signal with other devices. A MODE input is 2 used to control whether an E PROM will be used instead of a host microcontroller ...
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... VREFIN — The voltage reference input. Can be connected to VREFOUT or external 2.5 V refer- ence. VD+ — The positive digital supply. DGND — Digital ground. VA+ — The positive analog supply. AGND — Analog ground. NC — Factory use only. Connect to AGND. CS5464 Crystal In Serial Data Input Energy Output 2 Energy Output 1 Interrupt Reset ...
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... RMS Input Range 0.1% - 1.0% All Gain Ranges V RMS Input Range 5% - 100% CMRR (DC, 50, 60 Hz) (Gain = 10) IIN (Gain = 50) THD (Gain = 50) (50, 60 Hz) IC EII (Gain = 10 (Gain = 50 (Note 3) CS5464 Min Typ Max Unit 3.135 5.0 5.25 V 4.75 5 -40 - +85 °C Conditions. Min ...
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... Hz) sinewave is imposed onto the + supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to AGND. The CS5464 is then commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. ...
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... VREFOUT temperature coefficient VREF 9. Specified at maximum recommended output of 1 µA, source or sink. DS682F1 Symbol VREFOUT TC (Note 8) VREF ∆V (Note 9) VREFIN ( ( ( (VREFOUT - VREFOUT ) MAX MIN VREFOUT T AVG A MAX CS5464 Min Typ Max +2.4 +2.5 +2 +2.4 +2.5 +2 100 - ( ( ( ...
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... V IH XIN SCLK and RESET V IL XIN SCLK and RESET V IL XIN SCLK and RESET out (VD = +5V) OL out I = -2.5 mA (VD = +3.3V) out I (Note 16 out CS5464 Conditions. Min Typ Max 2.5 4.096 -5.4 - +5.4 - DCLK DCLK/1024 - - 0 100 1.0 0.6 VD (VD+) – 0.5 ...
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... Symbol t rise Any Digital Output t fall Any Digital Output t XTAL = 4.096 MHz (Note 11) ost SCLK t Pulse Width High 1 Pulse Width Low Pulse Width Low 9 Pulse Width High CS5464 Conditions. Min Typ Max Unit - - 1.0 µ 1.0 µ MHz 200 - - ns 200 - - 100 ...
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... and Figure 1. CS5464 Read and Write Timing Diagrams SDI Write Timing (Not to Scale) H igh B yte and SDO Read Timing (Not to Scale PROM mode Sequence Timing (Not to Scale) CS5464 yte Low B yte and and DS682F1 ...
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... V All Analog Pins INA V All Digital Pins IND stg Min Typ Max 500 - - 244 - - 1 248 - - Min Typ Max -0.3 - +6.0 -0 ± 100 - - 500 D - 0.3 - (VA+) + 0.3 -0.3 - (VD+) + 0.3 - -65 - 150 CS5464 Unit µs µs µs µs µs Unit °C °C 13 ...
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... For a sample rate of 4000 Hz, the delay range is ±250 µ phase shift of ±4.5° and ±5.4° Hz. The step size would be 0.0352° and 0.0422° this sample rate OFF GAIN I2 I2 OFF GAIN CS5464 DS682F1 ...
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... Cycle Count register. The low-rate interval is the sample interval multiplied and 4) re- 4.7 RMS Results The root mean square ( RMS in are performed on N instantaneous voltage and current samples, using the formula: CS5464 on page 19. The HPF filter multi- Figure 5) calculations N 1 – ∑ 2 ...
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... To use this feature, measure the average power at no load using either Single or Continuous Conversion com- mands. Take the measured result (from the register), invert (negate) the value and write it AVG to the associated power offset register, P1 Figure CS5464 , generated by inte- AVG AVG , I2 ) and peak voltage PEAK ...
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... PIN DESCRIPTIONS 5.1 Analog Pins The CS5464 has three differential inputs: VIN ±, IIN1 ± , and IIN2 ± are the voltage, current1, and current2 inputs, respectively. A single-ended power fail monitor input, voltage reference input, and voltage reference output are also available. ...
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... E PROMs. SDI is the serial data input to the CS5464. SDO is the serial data output from the CS5464. It’s out- put drivers are disabled whenever CS is de-asserted, al- lowing other devices to drive the SDO line the chip select input for the serial bus. A high logic level de-asserts it, tri-stating the SDO pin and clearing the serial interface ...
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... SETTING UP THE CS5464 6.1 Clock Divider The internal clock to the CS5464 needs to operate around 4 MHz. However, by using the internal clock di- vider, a higher crystal frequency can be used. This is im- portant when driving an external microcontroller requiring a faster clock and using the CPUCLK output. ...
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... The value is in output word rate (OWR) samples. The predetermined level is set by the values in the V1Sag LEVEL ( I2Fault LEVEL Since the values of V1 and V2 come from the same in- put, only one voltage sag detector is necessary. CS5464 ) is used to MIN and Q registers if PULSE PULSE register value. ...
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... For 60 Hz line frequency 60/4000 (0.015). Other output word rates (OWR) can be used. Epsilon can also be calculated automatically by the CS5464 by setting the AFC bit in the Mode Control ( Modes ) register. The Frequency Update bit (FUP) in the Status register is set every time the Epsilon register has been automatically updated ...
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... Modes register bit Ichan selects the energy channel, and is normally driven by the CS5464 pro- gram. This affects the pulse registers and pulse energy outputs. (See figure 8). The application program can also choose the more ap- propriate energy channel ...
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... Read and Write commands access one of 32 registers within a specified page. The Resgister Page Select reg- ister’s ( Page ) default value access registers in another page, write the desired page number to the Page register. The Page register is always at address 31 and is accessible from within any page. CS5464 23 ...
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... S0 0 The CS5464 has two power-down states, stand-by and sleep. In stand-by, all circuitry except the voltage ref- erence and clocks are turned off. In sleep, all circuitry except the command decoder is turned off. A Wake-up/Halt command restores full-power operation after stand-by and issues a hardware reset after sleep. ...
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... CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 The CS5464 can perform gain and offset calibrations using either signals. Proper input levels must be applied to the current inputs and voltage input before performing calibrations. CAL[5:4 Offset Gain Offset Gain CAL[3:0] 0001 = Current for Channel 1 ...
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... Power Factor Channel 1 Peak Current Channel 2 PEAK Peak Voltage Channel 2 PEAK Apparent Power Channel 2 Power Factor Channel 2 Interrupt Mask Temperature Control Active Energy Pulse Output PULSE Apparent Energy Pulse Output PULSE Reactive Energy Pulse Output PULSE Register Page Select CS5464 DS682F1 ...
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... System Time (in samples) Register Page Select Description V Sag Duration Channel 1 DUR V Sag Level Channel 1 LEVEL I Fault Duration Channel 1 DUR I Fault Level Channel 1 LEVEL V Sag Duration Channel 2 DUR V Sag Level Channel 2 LEVEL I Fault Duration Channel 2 DUR I Fault Level Channel 2 LEVEL Register Page Select CS5464 27 ...
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... Default = 0 Register Read and Write commands contain only 5 address bits. But the internal address bus of the CS5464 is 12 bits wide. Therefore, registers are organized into “Pages”. There are 128 pages of 32 registers each. The Page register provides the 7 high-order address bits and selects one of the 128 register pages. Not all pages are used, Page is a write-only integer containing 7 bits ...
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... AVG - -17 ..... and Voltage ( RMS RMS ), RMS RMS - -18 ..... contain the root mean square (RMS) values and calcu- RMS - -17 ..... AVG ) AVG - -17 ..... averaged over every N samples. These are two's complement AVG CS5464 -18 -19 -20 -21 - -18 -19 -20 -21 - -19 -20 -21 -22 - -18 -19 -20 -21 - -18 -19 -20 -21 - LSB -23 2 LSB ...
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... If the Ichan bit is “1”, these registers are driven from P2 AVG , V2 ) PEAK -18 -19 -20 - are the instantaneous current and voltage -18 -19 -20 - and I2 ), These are two's complement RMS RMS -18 -19 -20 - -11 -12 -13 - C), with the binary point to the right of bit 16. registers PULSE, PULSE, PULSE -18 -19 -20 - CS5464 LSB -22 - LSB -22 - LSB -22 - LSB -15 - LSB -22 - AVG DS682F1 ...
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... Invalid Command. Normally logic 1. Set to 0 when an invalid command is received. It may also indicate loss of serial command synchronization and the part may need to be re-initial- ized. DS682F1 CRDY I2ROR E1OR I1FAULT VOD I1OD CS5464 V2ROR I1OR V1OR V1SAG I2FAULT V2SAG LSD FUP IC ...
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... Saves power by disabling the CPUCLK output pin CPUCLK Enabled 1 = CPUCLK Disabled NOOSC Disables the crystal oscillator, making XIN a logic-level input Crystal Oscillator Enabled 1 = Crystal Oscillator Disabled PC5 PC4 PC3 I2gain - INTOD - 2 PROM command sequence (if used). CS5464 PC2 PC1 PC0 STOP NOCPU NOOSC - DS682F1 ...
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... During gain calibration GAIN GAIN ) OFF ) OFF - -17 ..... and Voltage (V1 ACOFF ACOFF ), ACOFF ACOFF - -17 ..... are initialized to zero on reset. These are added to ( & ) ACOFF ACOFF ACOFF , V2 ) OFF -18 -19 -20 - GAIN -17 -18 -19 - -18 -19 -20 - ACOFF ACOFF -18 -19 -20 - CS5464 LSB -22 - LSB -21 - LSB -22 - LSB -22 - ...
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... Ihold - E3MODE1 PULSE RMS . for energy channel selection AVG and P2 instead of I1 and I2 AVG RMS and I2 instead of P1 and P2 RMS AVG , P2 AVG AVG , Q 2 AVG AVG , CS5464 E2MODE1 E2MODE0 2 1 E3MODE0 POS , S , and Q registers. PULSE PULSE RMS . AVG . VHPF2 0 AFC DS682F1 ...
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... This is a two's complement value in the range of -1 ≤ value < 1, with the binary point to the left of the MSB. Refer to 6.10 Energy Pulse Rate DS682F1 Address: 17 – -17 ..... Address: 14 – ..... Address: 15 – -17 ..... page 20 for more information. CS5464 and negative value is AVG AVG -18 -19 -20 -21 - -18 -19 -20 -21 - LSB -23 2 LSB ...
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... LEVEL indicates no hysteresis will be used or Irms MIN MIN - ..... ..... -17 -18 -19 -20 - and P2 AVG . ) Address: 24 – -17 -18 -19 -20 - and P2 AVG AVG in use two's complement -17 -18 -19 -20 - Section 4.8 Power and Energy Results CS5464 LSB LSB -22 - AVG RMS LSB -22 - and RMS LSB -22 - DS682F1 ...
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... Address -17 ..... page 21 for more information. ) Address: 25 – SETTLE ..... Address 26 – MIN - -17 ..... register is less than Load PULSE ) Address 27 – RMS - -17 ..... CS5464 -12 -13 -14 -15 - -18 -19 -20 -21 - -18 -19 -20 -21 - register is less than Load PULSE Q , will be zeroed. pulse MIN -18 -19 -20 -21 - ...
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... V2Sag DUR ), 4 ( I1Fault ), 12 ( I2Fault DUR DUR ..... V2Sag ) and current fault duration DUR , V2Sag LEVEL ), 5 ( I1Fault ), 13 ( I2Fault LEVEL LEVEL - -17 ..... V2Sag ) and current fault level, I1Fault LEVEL CS5464 -17 -18 -19 -20 - I1Fault I2Fault DUR , DUR , DUR ) DUR I1Fault I2Fault ) determine the , ( DUR DUR ...
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... Since the voltage and current channels have indepen- dent offset and gain registers, offset and gain calibra- tion can be performed on any channel independently. The data flow of the calibration is shown in The CS5464 must be operating in its active state and ready to accept valid commands. Refer to mands on page 24. ...
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... Gain Calibration During gain calibration, a full-scale reference signal must be applied to the meter or optionally, scaled to the VIN ± , IIN1 ± (IIN2 ±) pins of the CS5464 reference must be used for DC gain calibration. Either reference can be used for RMS AC calibrations used, the associated high-pass filter (HPF) must be off ...
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... The CS5464 asserts CS (logic 0), clocks SCLK, and 2 sends Read commands to the E PROM on SDO. Command format is identical to microcontroller mode, except the CS5464 will not attempt to write to the EE de- vice. The command sequence stops when the STOP bit in the Control register ( Ctrl ) is written by the command sequence. VD ...
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... In this diagram, a shunt resistor is used to sense the line current and a voltage divider is used to sense the line voltage. In this type of shunt-resistor configuration, the common-mode level of the CS5464 must be referenced to the line side of the L2 L1 LINE 500 W ...
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... JEDEC #: MO-150 Controlling Dimension is Millimeters 1 E1 ∝ END VIEW L MILLIMETERS NOM MAX -- -- 2.13 0.15 0.25 1.75 1.88 -- 0.38 10.20 10.50 7.80 8.20 5.30 5.60 0.65 0.75 0.90 1.03 4° 8° CS5464 NOTE 2 ...
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... ORDERING INFORMATION Model CS5464-IS CS5464-ISZ (lead free) 14. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5464-IS CS5464-ISZ (lead free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 44 Temperature -40 to +85 °C Peak Reflow Temp MSL Rating* 240 °C 260 °C CS5464 Package 28-pin SSOP ...
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... JAN 2007 Update to correspond to rev C1 Silicon F1 MAR 2007 Updated capitalization of register names for consistency with CS5467. Updated Typical Connection diagram. Updated Phase Compensation Range from ±2.8° to ±5.4°. Updated document number to F1 for quality process level (QPL). DS682F1 CS5464 Changes 45 ...
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... AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 46 www.cirrus.com CS5464 DS682F1 ...