CS5463-ISZ Cirrus Logic Inc, CS5463-ISZ Datasheet - Page 33

• Manufacturer Part Number: CS5463-ISZ
• Description: IC ENERGY METERING 1PHASE 24SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5463-ISZ

• Package / Case: 24-SSOP
• Input Impedance: 30 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 0.8V
• Voltage - I/o Low: 0.2V
• Current - Supply: 2.9mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Meter Type: Single Phase
• Output Voltage Range: 2.4 V to 2.6 V
• Input Voltage Range: 2.4 V to 2.6 V
• Input Current: 25 nA
• Power Dissipation: 500 mW
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 5.25V
• No. Of Outputs: 3
• Power Dissipation Pd: 500mW
• Supply Voltage Range: 3.3V To 5V
• No. Of Pins: 24
• Filter Terminals: SMD
• Supply Voltage Min: 3.3V
• Rohs Compliant: Yes
• Frequency: 20GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1553 - BOARD EVAL & SOFTWARE CS5463 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1096-5

6.1.20 Control Register ( Ctrl )
6.1.21 Harmonic Active Power Register ( P
6.1.22 Fundamental Active Power Register ( P
DS678F2
MSB
MSB
-(2
-(2
STOP
INTOD
NOCPU
NOOSC
0
0
Default = 0x000000
Address: 29
The Harmonic Active Power (P
(Real) Power. The value is represented in two's complement notation and in the range of -1.0 ≤ P
the binary point to the right of the MSB.
Address: 30
The Fundamental Active Power (P
vant frequency on the V and I channels. The results are multiplied to yield fundamental power. The value is rep-
resented in two's complement notation and in the range of -1.0 ≤ P
the MSB.
)
)
23
15
7
Register Address: 28
2
2
-1
-1
2
2
-2
-2
22
14
0 = Normal (default)
1 = Stop sequence
0 = Normal (default)
1 = Open drain
0 = Normal (default)
1 = Disables CPUCLK
0 = Normal (default)
1 = Disabling oscillator circuit
Terminates the auto-boot sequence.
Converts INT output pin to an open drain output.
Saves power by disabling the CPUCLK pin.
Saves power by disabling the crystal oscillator.
6
2
2
-3
-3
2
2
-4
-4
21
13
5
H
) is calculated by subtracting the Fundamental Active Power from the Active
2
2
F
-5
-5
) is calculated by performing a discrete Fourier transform (DFT) at the rele-
2
2
-6
-6
INTOD
20
12
4
H
2
2
)
-7
-7
F
)
.....
.....
19
11
3
2
2
-17
-17
H
< 1.0, with the binary point to the right of
2
2
-18
-18
NOCPU
18
10
2
2
2
-19
-19
2
2
-20
-20
NOOSC
17
9
1
2
2
-21
-21
CS5463
H
2
2
-22
-22
< 1.0, with
STOP
16
8
0
LSB
LSB
2
2
-23
-23
33