CS5463-ISZ Cirrus Logic Inc, CS5463-ISZ Datasheet - Page 30

• Manufacturer Part Number: CS5463-ISZ
• Description: IC ENERGY METERING 1PHASE 24SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5463-ISZ

• Package / Case: 24-SSOP
• Input Impedance: 30 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 0.8V
• Voltage - I/o Low: 0.2V
• Current - Supply: 2.9mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Meter Type: Single Phase
• Output Voltage Range: 2.4 V to 2.6 V
• Input Voltage Range: 2.4 V to 2.6 V
• Input Current: 25 nA
• Power Dissipation: 500 mW
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 5.25V
• No. Of Outputs: 3
• Power Dissipation Pd: 500mW
• Supply Voltage Range: 3.3V To 5V
• No. Of Pins: 24
• Filter Terminals: SMD
• Supply Voltage Min: 3.3V
• Rohs Compliant: Yes
• Frequency: 20GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1553 - BOARD EVAL & SOFTWARE CS5463 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1096-5

6.1.12 Current and Voltage AC Offset Register ( V
6.1.13 Operational Mode Register ( Mode )
30
MSB
-(2
0
LSD
FUP
IC
Address: 16 (Current AC Offset); 17 (Voltage AC Offset)
Default = 0x000000
The AC Offset Registers (V
AC Offset Calibration updates these registers. This sequence lasts approximately (6N + 30) ADC cycles (where
N is the value of the Cycle Count Register ). DRDY will be asserted at the end of the calibration. These values
may be read and stored for future system AC offset compensation. The value is represented in two's comple-
ment notation in the range of -1.0 ≤ V
E2MODE
XVDEL
Address: 18
XIDEL
Default = 0x000000
XIDEL
)
23
15
7
2
-1
2
-2
IHPF
lates due to an input above full scale. The level at which the modulator oscillates is significantly
higher than the voltage channel’s differential input voltage (current) range.
Note: The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the
old (PMLO), with respect to AGND pin. The LSD bit cannot be reset until the voltage at PFMON
pin rises back above the high-voltage threshold (PMHI).
tus Register has not been successfully read.
22
14
the same time.
the same time.
Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage thresh-
Epsilon Updated. Indicates completion of a line frequency measurement and update of Epsilon.
Invalid Command. Normally logic 1. Set to logic 0 if an invalid command is received or the Sta-
E2 Output Mode
0 = Energy Sign (default)
1 = Apparent Power
Enables an extra sample of voltage channel delay. XVDEL and XIDEL can not be enabled at
Enables an extra sample of current channel delay. XVDEL and XIDEL can not be enabled at
6
2
-3
power line. This event should not be confused with a DC overload situation at the inputs,
when the IOD and VOD bits will re-assert themselves even after being cleared, multiple
times.
2
ACoff
-4
VHPF
, I
21
13
5
ACoff
2
-5
) are initialized to zero on reset, allowing for uncalibrated normal operation.
ACoff
, I
2
-6
ACoff
IIR
20
12
4
< 1.0, with the binary point to the right of the MSB
2
-7
ACoff
.....
E3MODE1
19
11
3
, I
2
-17
ACoff
2
E3MODE0
)
-18
18
10
2
2
-19
2
-20
E2MODE
POS
17
9
1
2
-21
CS5463
2
-22
XVDEL
DS678F2
AFC
16
8
0
LSB
2
-23