PCF85134HL/1,118 NXP Semiconductors, PCF85134HL/1,118 Datasheet - Page 15

• Manufacturer Part Number: PCF85134HL/1,118
• Description: IC LCD DISPLAY DRVR 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF85134HL/1,118

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Digits Or Characters: Any Digit Type
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5060-2

NXP Semiconductors
PCF85134_1
Product data sheet
7.10 Display RAM
7.9 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated based on the selected LCD drive mode.
If less than four backplane outputs are required the unused outputs can be left
open-circuit.
The display RAM is a static 60
bit map indicates the on-state of the corresponding LCD element; similarly, a logic 0
indicates the off-state. There is a one-to-one correspondence between the RAM
addresses and the segment outputs and between the individual bits of a RAM word and
the backplane outputs. The display RAM bit map,
correspond with the backplane outputs BP0 to BP3, and columns 0 to 59 which
correspond with the segment outputs S0 to S59. In multiplexed LCD applications the
segment data of the first, second, third, and fourth row of the display RAM are
time-multiplexed with BP0, BP1, BP2, and BP3 respectively.
When display data is transmitted to the PCF85134, the received display bytes are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for the acknowledge cycle as with the commands. Depending
on the current multiplex drive mode, data is stored singularly, in pairs, triples, or
quadruples. To illustrate the filling order, an example of a 7-segment display showing all
drive modes is given in
other LCD types.
Fig 9.
•
•
•
•
In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
In static drive mode: The same signal is carried by all four backplane outputs; and
they can be connected in parallel for very high drive requirements.
display RAM rows/
backplane outputs
The display RAM bit map shows the direct relationship between the display RAM addresses and
the segment outputs and between the bits in a RAM word and the backplane outputs.
Display RAM bit map
rows
(BP)
Rev. 01 — 17 December 2009
0
1
2
3
Figure
0
1
10; the RAM filling organization depicted applies equally to
2
4 bit RAM which stores LCD data. A logic 1 in the RAM
3
display RAM addresses/segment outputs (S)
4
Universal LCD driver for low multiplex rates
columns
Figure
9, shows rows 0 to 3 which
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PCF85134
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© NXP B.V. 2009. All rights reserved.
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