MAX8731AETI+ Maxim Integrated Products, MAX8731AETI+ Datasheet - Page 27

• Manufacturer Part Number: MAX8731AETI+
• Description: IC SMBUS LVL2 BATT CHRGR 28TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8731AETI+

• Function: Charge Management
• Battery Type: Multi-Chemistry
• Voltage - Supply: 8 V ~ 26 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN Exposed Pad
• Product: Charge Management
• Output Voltage: 5.4 V
• Operating Supply Voltage: 8 V to 26 V
• Supply Current: 2 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Charge Safety Timers: Yes
• Mounting Style: SMD/SMT
• Temperature Monitoring: No
• Uvlo Start Threshold: 2.5 V
• Uvlo Stop Threshold: 100 mV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The crossover frequency is given by:
For stability, choose a crossover frequency lower than
1/10 the switching frequency:
Choosing a crossover frequency of 30kHz and using
the component values listed in
5.4nF. Values for CCS greater than 10 times the mini-
mum value may slow down the current-loop response
excessively.
current-limit-loop frequency response using the values
calculated above.
The DHI and DLO outputs are optimized for driving
moderate-sized power MOSFETs. The MOSFET drive
capability is the same for both the low-side and high-
sides switches. This is consistent with the variable duty
factor that occurs in the notebook computer environ-
ment where the battery voltage changes over a wide
range. There must be a low-resistance, low-inductance
path from the DLO driver to the MOSFET gate to pre-
vent shoot-through. Otherwise, the sense circuitry in the
MAX8731A interprets the MOSFET gate as “off” while
there is still charge left on the gate. Use very short,
wide traces measuring 10 to 20 squares or less
(1.25mm to 2.5mm wide if the MOSFET is 25mm from
Figure
12. CCS Loop Response
100
-20
-40
80
60
40
20
0
0.1
Figure 12
C
CS
f
CO CS
______________________________________________________________________________________
= ×
10
_
5
shows the Bode plot of the input
FREQUENCY (Hz)
GMS
=
2π
1k
GMS
/(
C
2
SMBus Level 2 Battery Charger
CS
π
Figure 1
f
OSC
100k
MOSFET Drivers
MAG
PHASE
)
yields C
10M
0
-45
-90
CS
>
the device). Unlike the DLO output, the DHI output uses
a 50ns (typ) delay time to prevent the low-side MOSFET
from turning on until DHI is fully off. The same consider-
ations should be used for routing the DHI signal to the
high-side MOSFET.
The high-side driver (DHI) swings from LX to 5V above
LX (BST) and has a typical impedance of 3Ω sourcing
and 1Ω sinking. The low-side driver (DLO) swings from
DLOV to ground and has a typical impedance of 1Ω
sinking and 3Ω sourcing. This helps prevent DLO from
being pulled up when the high-side switch turns on, due
to capacitive coupling from the drain to the gate of the
low-side MOSFET. This places some restrictions on the
MOSFETs that can be used. Using a low-side MOSFET
with smaller gate-to-drain capacitance can prevent
these problems.
Choose the n-channel MOSFETs according to the maxi-
mum required charge current. The MOSFETs must be
able to dissipate the resistive losses plus the switching
losses at both V
For the high-side MOSFET, the worst-case resistive
power losses occur at the maximum battery voltage
and minimum supply voltage:
Generally a low-gate charge high-side MOSFET is pre-
ferred to minimize switching losses. However, the
R
pation limits often limits how small the MOSFET can be.
The optimum occurs when the switching (AC) losses
equal the conduction (R
power dissipation in N1 due to switching losses is diffi-
cult since it must allow for difficult quantifying factors
that influence the turn-on and turn-off times. These fac-
tors include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PCB layout
characteristics. The following switching-loss calculation
provides a rough estimate and is no substitute for
breadboard evaluation, preferably including a verifica-
tion using a thermocouple mounted on N1:
PD
PD
DS(ON)
with Remote Sense
SWITCHING
CONDUCTION
required to stay within package power-dissi-
(
High Side
DCIN(MIN)
(
HighSide
) =
DS(ON)
and V
2
1
)
Design Procedure
=
×
t
V
V
Trans
) losses. Calculating the
CSSP
MOSFET Selection
FBS
DCIN(MAX)
_
×
V
×
DCIN
I
CHG
.
×
2
I
CHG
×
R
DS ON
×
(
f
SW
27
)