ISL94201IRZ Intersil, ISL94201IRZ Datasheet - Page 14

• Manufacturer Part Number: ISL94201IRZ
• Description: IC MULTI LI-ION AFE 24-QFN
• Manufacturer: Intersil

Specifications of ISL94201IRZ

• Function: Over/Under Voltage Protection
• Battery Type: Lithium-Ion (Li-Ion)
• Voltage - Supply: 5 V ~ 10 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The device responds with an acknowledge after recognition
of a start condition and the correct slave byte. If a write
operation is selected, the device responds with an
acknowledge after the receipt of each subsequent eight bits.
The device acknowledges all incoming data and address
bytes, except for the slave byte when the contents do not
match the device’s internal slave address.
In the read mode, the device transmits eight bits of data,
releases the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will
continues to transmit data. The device terminates further
data transmissions if an acknowledge is not detected. The
master must then issue a stop condition to return the device
to Standby mode and place the device into a known state.
.
FROM RECEIVER
TRANSMITTER
SCL
SDA
DATA OUTPUT
DATA OUTPUT
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
SDA
SCL
SCL FROM
MASTER
FIGURE 6. VALID DATA CHANGES ON I
FROM
FIGURE 7. I
STABLE
START
DATA
START
2
C START AND STOP BITS
1
CHANGE
14
DATA
STABLE
DATA
8
STOP
ACKNOWLEDGE
2
C BUS
9
ISL94201
WRITE OPERATIONS
For a write operation, the device requires a slave byte and
an address byte. The slave byte specifies the particular
device on the I
address specifies one of the registers in that device. After
receipt of each byte, the device responds with an
acknowledge, and awaits the next eight bits from the master.
After the acknowledge, following the transfer of data, the
master terminates the transfer by generating a stop
condition. See Figure 9.
When receiving data from the master, the value in the data
byte is transferred into the register specified by the address
byte on the falling edge of the clock following the 8th data bit.
After receiving the acknowledge after the data byte, the
device automatically increments the address. So, before
sending the stop bit, the master may send additional data to
the device without re-sending the slave and address bytes.
After writing to address 0AH, the address “wraps around” to
address 0. Do not continue to write to addresses higher than
address 08H, since these addresses access registers that
are reserved. Writing to these locations can result in
unexpected device operation.
SDA BUS
A
R
S
T
T
0 1 0 1
2
SLAVE
C bus that the master is writing to. The
FIGURE 9. WRITE SEQUENCE
BYTE
0
0 0
ISL94201: SLAVE BYTE = 50H
0
A
C
K
REGISTER
ADDRESS
A
C
K
DATA
July 3, 2008
FN6719.0
A
C
K
S
O
P
T