DP8422AV-20 National Semiconductor, DP8422AV-20 Datasheet - Page 46

• Manufacturer Part Number: DP8422AV-20
• Description: IC CTRLR/DVR CMOS PROGRAM 84PLCC
• Manufacturer: National Semiconductor

Specifications of DP8422AV-20

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8422AV-20

Number
100
101
102
103
105
106
107
108
109
110
111
112
113
114
116
117
118a
118b
118c
118d
120a
120b
120c
120d
121
13 0 AC Timing Parameters
Unless otherwise stated V
per bank including trace capacitance (Note 2)
Two different loads are specified
C
C
L
L
e
e
50 pF loads on all outputs except
150 pF loads on Q0–8 9 10 and WE or
tHCKARQB
tSARQBCK
tPAQBRASL
tPAQBRASH
tPCKRASG
tPAQBATKBL AREQB Asserted to ATACKB Asserted
tPCKATKB
tPCKGH
tPCKGL
tSADDCKG
tSLOCKCK
tPAQATKBH
tPAQBCASH
tSADAQB
tHCKARQG
tWAQB
tPAQBCAS0
tPAQBCAS1
tPAQBCAS2
tPAQBCAS3
tPCKCASG0
tPCKCASG1
tPCKCASG2
tPCKCASG3
tSBADDCKG
Symbol
AREQB Negated Held from CLK High
AREQB Asserted Setup to CLK High
AREQB Asserted to RAS Asserted
AREQB Negated to RAS Negated
CLK High to RAS Asserted for
Pending Port B Access
CLK High to ATACKB Asserted
for Pending Access
CLK High to GRANTB Asserted
CLK High to GRANTB Negated
Row Address Setup to CLK High That
Asserts RAS following a GRANTB
Change to Ensure tASR
LOCK Asserted Setup to CLK Low
to Lock Current Port
AREQ Negated to ATACKB Negated
AREQB Negated to CAS Negated
Address Valid Setup to
AREQB Asserted
AREQ Negated Held from CLK High
AREQB High Pulse Width
to Guarantee tASR
AREQB Asserted to CAS Asserted
(tRAH
AREQB Asserted to CAS Asserted
(tRAH
AREQB Asserted to CAS Asserted
(tRAH
AREQB Asserted to CAS Asserted
(tRAH
CLK High to CAS Asserted
for Pending Port B Access
(tRAH
CLK High to CAS Asserted
for Pending Port B Access
(tRAH
CLK High to CAS Asserted
for Pending Port B Access
(tRAH
CLK High to CAS Asserted
for Pending Port B Access
(tRAH
Bank Address Valid Setup to CLK
High That Starts RAS
for Pending Port B Access
CC
e
e
e
e
e
e
e
e
e
5 0V
Parameter Description
Common Dual Access
15 ns tASC
15 ns tASC
25 ns tASC
25 ns tASC
15 ns tASC
15 ns tASC
25 ns tASC
25 ns tASC
g
10% 0 C
e
(Continued)
e
e
e
e
e
e
e
e
0 ns
e
k
0 ns)
10 ns)
0 ns)
10 ns)
0 ns)
10 ns)
0 ns)
10 ns)
0 ns for Port B
T
A k
70 C the output load capacitance is typical for 4 banks of 18 DRAMs
46
C
C
C
H
H
H
Min
11
31
10
3
8
5
7
5
e
e
e
8420A 21A 22A-20
C
50 pF loads on all outputs except
125 pF loads on RAS0– 3 and CAS0–3 and
380 pF loads on Q0– 8 9 10 and WE
L
Max
103
113
113
123
113
123
123
133
43
41
55
57
67
40
35
26
59
Min
15
11
35
10
3
8
5
5
C
H
Max
111
121
121
131
121
131
131
141
48
46
60
57
67
40
35
26
67
Min
11
26
10
3
7
5
7
5
8420A 21A 22A-25
C
L
Max
107
106
106
116
37
32
44
45
51
32
29
21
47
87
97
97
96
Min
16
12
31
10
3
7
5
5
C
H
Max
104
104
114
103
113
113
123
41
36
48
45
51
32
29
21
54
94