DP8422AV-20 National Semiconductor, DP8422AV-20 Datasheet - Page 36

• Manufacturer Part Number: DP8422AV-20
• Description: IC CTRLR/DVR CMOS PROGRAM 84PLCC
• Manufacturer: National Semiconductor

Specifications of DP8422AV-20

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8422AV-20

8 0 Test Mode
Staggered refresh in combination with the error scrubbing
mode places the DP8420A 21A 22A in test mode In this
mode the 24-bit refresh counter is divided into a 13-bit and
11-bit counter During refreshes both counters are incre-
mented to reduce test time
9 0 DRAM Critical Timing
Parameters
The two critical timing parameters shown in Figure 31 that
must be met when controlling the access timing to a DRAM
are the row address hold time t
dress setup time t
tain a precise internal delay line the values of these param-
eters can be selected at programming time These values
will also increase and decrease if DELCLK varies from
2 MHz
9 1 PROGRAMMABLE VALUES OF t
The DP8420A 21A 22A allow the values of t
to be selected at programming time For each parameter
two choices can be selected t
time is measured from RAS asserted to the row address
starting to change to the column address The two choices
for t
dress bit C8
t
column address valid to CAS asserted The two choices for
t
C7
ASC
ASC
RAH
are 0 ns and 10 ns programmable through address bit
the column address setup time is measured from the
are 15 ns and 25 ns programmable through ad-
ASC
Since the DP8420A 21A 22A con-
RAH
RAH
the row address hold
RAH
and the column ad-
AND t
RAH
ASC
FIGURE 31 t
and t
ASC
36
RAH
9 2 CALCULATION OF t
There are two clock inputs to the DP8420A 21A 22A
These two clocks DELCLK and CLK can either be tied to-
gether to the same clock or be tied to different clocks run-
ning asynchronously at different frequencies
The clock input DELCLK controls the internal delay line
and refresh request clock DELCLK should be a multiple of
2 MHz If DELCLK is not a multiple of 2 MHz t
will change The new values of t
lated by the following formulas
If t
30 (((DELCLK Divisor) 2 MHz (DELCLK Frequency))
If t
30 (((DELCLK Divisor) 2 MHz (DELCLK Frequency))
If t
((DELCLK Divisor) 2 MHz (DELCLK Frequency))
If t
((DELCLK Divisor) 2 MHz (DELCLK Frequency))
Since the values of t
creased the time to CAS asserted will also increase or de-
crease These parameters can be adjusted by the following
formula
Delay to CAS
Programmed t
a
a
and t
ASC
ASC
15 ns
25 ns
RAH
RAH
ASC
was programmed to equal 10 ns then t
was programmed to equal 0 ns then t
was programmed to equal 15 ns then t
was programmed to equal 25 ns then t
e
RAH
Actual Spec
a
Actual t
RAH
RAH
and t
ASC
AND t
a
RAH
Actual t
ASC
b
ASC
Programmed t
and t
TL F 8588 – E3
are increased or de-
RAH
ASC
b
RAH
can be calcu-
ASC
ASC
b
b
ASC
and t
RAH
RAH
e
e
15 ns
15 ns
b
b
ASC
15
25
e
e
1)
1)