XC17256EPC20C Xilinx Inc, XC17256EPC20C Datasheet - Page 4

• Manufacturer Part Number: XC17256EPC20C
• Description: IC SERIAL CFG PROM 256K 20-PLCC
• Manufacturer: Xilinx Inc

Specifications of XC17256EPC20C

• Programmable Type: OTP
• Memory Size: 256Kb
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1203; XC17256EJC

Xilinx FPGAs and Compatible PROMs
DS027 (v3.5) June 25, 2008
Product Specification
XC4036EX/XL/XLA
XC4013XL/XLA
XC4020XL/XLA
XC4028XL/XLA
XC4044XL/XLA
XC4052XL/XLA
XC4062XL/XLA
XC4085XL/XLA
XC40110XV
XC40150XV
XC40200XV
XC40250XV
XC4028EX
XC4036EX
XC4002XL
XC4005XL
XC4010XL
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
XCV1000
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XC5202
XC5204
XC5206
XC5210
XC5215
Device
XCV50
R
Configuration
Product Obsolete or Under Obsolescence
1,014,928
1,215,368
1,433,864
1,924,992
2,686,136
3,373,448
4,551,056
5,433,888
1,040,096
1,335,840
1,751,808
2,546,048
3,607,968
4,715,616
6,127,744
119,840
147,552
178,144
247,968
329,312
422,176
151,960
283,424
393,632
521,880
668,184
668,184
832,528
832,528
106,288
165,488
237,744
559,200
781,216
53,984
95,008
61,100
42,416
70,704
Bits
XC17128EL
XC17128E
XC17256EL
XC1704L +
XC1704L +
XC1704L +
XC17128E
XC17128E
XC17256E
XC17128E
XC17128E
XC17256E
XC17256E
XC17512L
XC17512L
XC17512L
XC17512L
XC1704L+
XC17256E
XC17256E
XC1765E
XC1701L
XC1701L
XC1701L
XC1702L
XC1702L
XC1702L
XC1704L
XC1704L
XC1702L
XC1701L
XC1701L
XC1701L
XC1702L
XC1702L
XC1704L
XC1704L
XC1701L
XC1702L
XC1701
XC1701
XC1701
XC1701
PROM
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
www.xilinx.com
(1)
(1)
Controlling PROMs
Connecting the FPGA device with the PROM:
•
•
•
•
•
•
Notes:
1.
The DATA output(s) of the of the PROM(s) drives the
D
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V
Other methods—such as driving RESET/OE from LDC
or system reset—assume the PROM internal power-
on-reset is always in step with the FPGA’s internal
power-on-reset. This may not be a safe assumption.
The PROM CE input can be driven from either the LDC
or DONE pins. Using LDC avoids potential contention
on the D
The CE input of the lead (or only) PROM is driven by
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC can be used to drive CE, but must then be
unconditionally High during user operation. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
The suggested PROM is determined by compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.
Designers using the default slow configuration frequency (CCLK)
can use the XC1765E or XC1765EL for the noted FPGA devices.
IN
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
XCV100E
XCV200E
XCV300E
XCV400E
XCV405E
XCV600E
XCV812E
XCV50E
Device
input of the lead FPGA device.
IN
pin.
Configuration
10,159,648
12,922,336
16,283,712
1,442,016
1,875,648
2,693,440
3,340,400
3,961,632
6,519,648
6,587,520
8,308,992
630,048
863,840
Bits
2 of XC1704L
2 of XC1704L
2 of XC1704L
3 of XC1704L
4 of XC1704L
4 of XC1704L
CC
XC1701L
XC1701L
XC1702L
XC1702L
XC1704L
XC1704L
XC1704L
PROM
glitch.
4