XC17256EPC20C Xilinx Inc, XC17256EPC20C Datasheet - Page 2

• Manufacturer Part Number: XC17256EPC20C
• Description: IC SERIAL CFG PROM 256K 20-PLCC
• Manufacturer: Xilinx Inc

Specifications of XC17256EPC20C

• Programmable Type: OTP
• Memory Size: 256Kb
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1203; XC17256EJC

Pin Description
DATA
Data output is in a high-impedance state when either CE or
OE are inactive. During programming, the DATA pin is I/O.
Note that OE can be programmed to be either active High or
active Low.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The
polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this
document describes the pin as RESET/OE, although the
opposite polarity is possible on all devices. When RESET is
active, the address counter is held at "0", and puts the DATA
output in a high-impedance state. The polarity of this input
is programmable. The default is active High RESET, but the
preferred option is active Low RESET, because it can be
driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer
interface. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have
different methods to invert this pin.
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-I
CEO
Chip Enable output, to be connected to the CE input of the next
PROM in the daisy chain. This output is Low when the CE and
OE inputs are both active AND the internal address counter
has been incremented beyond its Terminal Count (TC) value.
In other words: when the PROM has been read, CEO follows
CE as long as OE is active. When OE goes inactive, CEO
stays High until the PROM is reset. Note that OE can be
programmed to be either active High or active Low.
V
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read
DS027 (v3.5) June 25, 2008
Product Specification
PP
R
CC
standby mode.
Product Obsolete or Under Obsolescence
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
www.xilinx.com
operation, this pin must be connected to V
so may lead to unpredictable, temperature-dependent
operation and severe problems in circuit debugging. Do not
leave V
V
Positive supply and ground pins.
PROM Pinouts
Pins not listed are "no connects."
"
Capacity
DATA
CLK
RESET/OE
(OE/RESET)
CE
GND
CEO
V
V
CC
Pin Name
PP
CC
XC17128E/EL
XC17256E/EL
XC1765E/EL
and GND
XC17512L
XC1701/L
XC1736E
XC1704L
XC1702L
Devices
PP
floating!
PDG8 )
SOG8)
VOG8)
(PD8/
(SO8/
(VO8/
8-pin
PDIP
SOIC
VOIC
1
2
3
4
5
6
7
8
(SO20)
20-pin
SOIC
10
11
13
18
20
1
3
8
Configuration Bits
PCG20)
(PC20/
20-pin
PLCC
10
14
17
20
2
4
6
8
4,194,304
2,097,152
1,048,576
524,288
131,072
262,144
36,288
65,536
CC
(VQ44)
44-pin
VQFP
18, 41
40
43
13
15
21
35
38
. Failure to do
(PC44)
44-pin
PLCC
24, 3
19
21
27
41
44
2
5
2