AT17C010-10JI Atmel, AT17C010-10JI Datasheet - Page 4

• Manufacturer Part Number: AT17C010-10JI
• Description: IC SERIAL CONFIG PROM 1M 20PLCC
• Manufacturer: Atmel

Specifications of AT17C010-10JI

• Programmable Type: Serial EEPROM
• Memory Size: 1Mb
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT17C01010JI

Pin Description
Note:
4
PDIP/
LAP
Pin
8
1
2
3
4
5
6
7
8
1. This pin is not available on the 8-lead packages.
AT17C512/010/LV512/010
PLCC
Pin
20
10
14
15
17
20
2
4
5
6
7
8
RESET/OE
READY
SER_EN
WP1
WP2
Name
DATA
GND
CEO
CLK
V
CE
A2
CC
(1)
(1)
(1)
I/O
I/O
O
O
I
I
I
I
I
I
I
Description
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
WRITE PROTECT (1). Used to protect portions of memory during programming.
Disabled by default due to internal pull-down resistor. This input pin is not used
during FPGA loading operations.
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable
as either RESET/OE or RESET/OE. For most applications, RESET should be
programmed active Low. This document describes the pin as RESET/OE.
WRITE PROTECT (2). Used to protect portions of memory during programming.
Disabled by default due to internal pull-down resistor. This input pin is not used
during FPGA loading operations.
Chip Enable input (active Low). A Low level (with OE High) allows DCLK to
increment the address counter and enables the data output driver. A High level on
CE disables both the address and bit counters and forces the device into a low-
power standby mode. Note that this pin will not enable/disable the device in the 2-
wire Serial Programming mode ( SER_EN Low).
Ground pin. A 0.2 µF decoupling capacitor between
recommended.
Chip Enable Output (active Low). This output goes Low when the address counter
has reached its maximum value. In a daisy chain of AT17 Series devices, the CEO
pin of one device must be connected to the CE input of the next device in the chain.
It will stay Low as long as CE is low and OE is High. It will then follow CE until OE
goes Low; thereafter, CEO will stay High until the entire EEPROM is read again.
Device selection input, A2. This is used to enable (or select) the device during
programming (i.e., when SER_EN is Low). A2 has an internal pulldown resistor.
Open collector reset state indicator. Driven Low during power-up reset, released
(tri-stated) when power-up is complete. (Recommend a 4.7 kΩ pull-up on this pin if
used).
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the 2-wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to V
+3.3V/+5V power supply pin.
CC
.
V
CC
and GND is
0944E–12/01