AT17C010-10JI Atmel, AT17C010-10JI Datasheet - Page 3

• Manufacturer Part Number: AT17C010-10JI
• Description: IC SERIAL CONFIG PROM 1M 20PLCC
• Manufacturer: Atmel

Specifications of AT17C010-10JI

• Programmable Type: Serial EEPROM
• Memory Size: 1Mb
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT17C01010JI

Block Diagram
Device Description
0944E–12/01
POWER ON
CONTROL
RESET
OSC
OSC
SER_EN
WP2
WP1
CLK READY
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17 Series Configurator. If CE is held High after the
RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated.
When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET/OE.
PROGRAMMING
COUNTER
COUNTER
ADDRESS
MODE LOGIC
ROW
RESET/OE
BIT
CE
DECODER
AT17C512/010/LV512/010
ROW
TC
CEO(A2)
PROGRAMMING
DECODER
DATA SHIFT
COLUMN
REGISTER
EEPROM
MATRIX
CELL
DATA
3