RC28F128K3C115 Intel, RC28F128K3C115 Datasheet - Page 48

• Manufacturer Part Number: RC28F128K3C115
• Description: IC FLASH 128MBIT 115NS 64BGA
• Manufacturer: Intel

Specifications of RC28F128K3C115

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 128M (8Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 848521

28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
11.5.2
11.5.3
48
Warning:
Note: If the number of words is less than 32, as in the case of the last page program sequence for a block,
Buffered-EFP considerations:
1
A[
2
to work properly.
3
to the beginning of the block.
4
locations must be filled with FFFFh. The responsibility to manage this falls within the programming
equipment, not the customer data file.
See
detailed flowchart of the Buffered-EFP operation.
Buffered-EFP Setup Phase
After receiving the Buffered-EFP Setup (80h) and Confirm (D0h) command sequence, device SR.7
transitions from a ‘1’ to a ‘0,’ indicating that the WSM is busy with the Buffered-EFP algorithm
startup. A delay before checking SR.7 is required to allow the WSM time to perform all of its
setups and checks (block lock status and V
Buffered-EFP operation terminates. If the block was found locked, SR.1 is also set. SR.3 is set if
the error occurred due to the V
Buffered-EFP Program and Verify Phase
After setup completion, the host programming system must check SR.0 to determine “data-stream
ready” status. SR.0=0 indicates that the Buffered-EFP program/verify phase is activated and the
write buffer is available.
Two basic sequences repeat in this phase: loading the write buffer, followed by buffer data
programming to the array. For Buffered-EFP, the count value for buffer loading is always the
maximum buffer size of 32 words. During the page loading sequence, data received is stored to
sequential buffer locations starting at address 00h. Programming of that page to the flash array
starts immediately when the buffer is full.
The buffer must be completely full for programming to occur. Supplying an address outside the
current block’s range during a buffer fill sequence will cause the operation to lockup.
remaining locations must be filled with FFFFh. The responsibility to manage this falls within the
programming equipment, not the customer data file.
Data words from the write buffer are directed to sequential memory locations in the array,
programming takes up where the last page sequence left off. The host programming system must
poll SR.0 to determine when the page program sequence completes. SR.0=0 indicates that all
Buffer boundary in array is determined by A[
Some degradation in performance may occur if this limit is exceeded, but the internal algorithm will continue
If the internal address counter increments beyond the block’s maximum address, addressing will wrap around
If the number of words is less than 32, as in the case of the last page program sequence for a block, remaining
•
•
•
•
A
MIN
Figure 28, “Buffered Enhanced Factory Programming Procedure Flowchart” on page
For optimum performance, limit cycling below 100 erase cycles per block
Buffered-EFP programs one block at a time, all buffer data must fall within a single block
Buffered-EFP cannot be suspended
Programming to flash can only occur when the buffer is full
+4:A
MIN
]=0.
PEN
level being incorrect.
A
PEN
MIN
level). If an error is detected, SR.4 is set and
+4:A
MIN
] (00h through 1Fh). Alignment start point is
4
2
Datasheet
73, for a
3