RC28F128K3C115 Intel, RC28F128K3C115 Datasheet - Page 20

• Manufacturer Part Number: RC28F128K3C115
• Description: IC FLASH 128MBIT 115NS 64BGA
• Manufacturer: Intel

Specifications of RC28F128K3C115

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 128M (8Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 848521

28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
4.4
20
A[A
D[15:0]
MAX
VCCQ
VPEN
VSSQ
Table 4.
RST#
ADV#
WAIT
Sym
WE#
WP#
VCC
CE#
OE#
CLK
STS
VSS
RFU
DU
NC
:A
MIN
]
Open Drain
Signal Descriptions
Table 4
Signal Descriptions
Output
Output
Output
Power
Power
Power
Power
Input/
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
—
—
—
describes the active signals used.
ADDRESS: Device address. Address internally latched during read/write operations. See
nomenclature Section 1.2 for A
DATA I/O: Inputs data and commands during write operations, outputs data during read
operations. Float when CE# or OE# are de-asserted. Data is internally latched during write
operations.
CHIP ENABLE: Active-low; CE#-low selects the device. CE#-high deselects the device, places it
in standby mode, and places data and WAIT outputs in a High-Z state.
OUTPUT ENABLE: Active-low; OE#-low enables the device’s output data drivers during read
cycles. OE#-high places the data outputs in a High-Z state.
WRITE ENABLE: Active-low; WE# controls writes to the flash device. Address and data are
latched on the rising edge of WE#.
RESET: Active-low; resets internal circuitry and inhibits write operations. This provides data
protection during power transitions. RST#-high enables normal operation. Exit from reset places
the device in asynchronous read-array mode.
WRITE PROTECT: Active-low; WP#-low enables the lock-down mechanism. Blocks locked
down cannot be unlocked with the unlock command. WP#-high overrides the lock-down function
enabling blocks to be erased or programmed through software.
ADDRESS VALID: Active-low; during synchronous read operations, addresses are latched on
the rising edge of ADV# or on the rising (or falling) edge of CLK, whichever occurs first.
ERASE/PROGRAM/BLOCK LOCK ENABLE: Controls device protection. When V
V
CLOCK: Synchronizes the device to the system’s bus frequency in synchronous-read mode,
and increments the internal address generator. During synchronous read operations, addresses
are latched on ADV#’s rising edge or CLK’s rising (or falling) edge, whichever occurs first.
Connect this signal to VCC if the device will not be used in synchronous-read mode.
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default mode), it acts as a RY/BY# pin. When configured in one of its pulse modes, it can
indicate program and/or erase completion. For alternate configurations of the STATUS pin, see
the configuration commands. STS is to be tied to V
WAIT: Indicates invalid data in synchronous-read (burst) modes. WAIT is High-Z whenever CE#
is de-asserted. WAIT is not gated by OE#.
CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when V
I/O POWER SUPPLY: I/O Output-driver source voltage.
GROUND: Ground reference for device core power supply. Connect to system ground.
I/O GROUND: I/O Ground reference for device I/O power supply. Connect to system ground.
DO NOT USE: Do not use this ball. This ball should not be connected to any power supplies,
signals or other balls and must be left floating.
NO CONNECT: No internal connection; can be driven or floated.
RESERVED for FUTURE USE: Balls designated as RFU are reserved by Intel for future device
functionality and enhancement.
PENLK
, flash contents are protected against Program and Erase.
CC
≤ V
LKO
. Device operation at invalid V
MAX
and A
Name and Function
MIN
values.
CC
CCQ
voltages should not be attempted.
with a pull-up resistor.
PEN
Datasheet
≤