M24C64-RMB6TG STMicroelectronics, M24C64-RMB6TG Datasheet - Page 16

• Manufacturer Part Number: M24C64-RMB6TG
• Description: IC EEPROM 64KBIT 400KHZ 8MLP
• Manufacturer: STMicroelectronics

Specifications of M24C64-RMB6TG

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-MLP, 8-UFDFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device operation
4.6
4.7
4.8
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Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data Byte.
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant
Byte
form the address of the byte in memory.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10
cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write
cycle.
After the Stop condition, the delay t
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in
Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same ‘row’ in the memory: that is, the most significant
memory address bits (b12-b5) are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (inside the page) is
incremented. The transfer is terminated by the bus master generating a Stop condition.
(Table
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
3) is sent first, followed by the Least Significant Byte
Doc ID 16891 Rev 23
W
, and the successful completion of a Write operation,
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
Figure
10.
Figure
Figure
(Table
9.
10, and waits for two
4). Bits b15 to b0