CY7C1270V18-375BZXC Cypress Semiconductor Corp, CY7C1270V18-375BZXC Datasheet - Page 6

• Manufacturer Part Number: CY7C1270V18-375BZXC
• Description: IC SRAM 36MBIT 375MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1270V18-375BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 36M (1M x 36)
• Speed: 375MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Document Number: 001-06347 Rev. *D
DQ
LD
NWS
BWS
BWS
A
R/W
QVLD
K
K
CQ
CQ
Pin Name
[x:0]
0
2
0
, BWS
, BWS
, NWS
1
3
1
,
Input/Output-
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
Valid Output
Indicator
Input-
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Clock
IO
Data Input/Output Signals. Inputs are sampled on the rising edge of K and K clocks during
valid write operations. These pins drive out the requested data during a read operation. Valid
data is driven out on the rising edge of both the K and K clocks during read operations. When
read access is deselected, Q
CY7C1266V18 – DQ
CY7C1277V18 – DQ
CY7C1268V18 – DQ
CY7C1270V18 – DQ
Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when
a bus cycle sequence is to be defined. This definition includes address and read/write direction.
All transactions operate on a burst of 2 data. LD must meet the setup and hold times around
edge of K.
Nibble Write Select 0, 1, Active LOW (CY7C1266V18 only). Sampled on the rising edge of
the K and K clocks during write operations. Used to select which nibble is written into the device
during the current portion of the write operations. Nibbles not written remain unaltered.
NWS
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select ignores the corresponding nibble of data and not written into the device.
Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks
during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1277V18 − BWS
CY7C1268V18 − BWS
CY7C1270V18 − BWS
controls D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select ignores the corresponding byte of data and not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active read and write opera-
tions. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1266V18, 4M x 9 (2 arrays
each of 2M x 9) for CY7C1277V18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1268V18, and
1M x 36 (2 arrays each of 512K x 36) for CY7C1270V18.
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read
when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the setup and
hold times around edge of K.
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ
and CQ.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous data being presented to the
device and to drive out data through Q
input clock (K) of the DDR-II+. The timing for the echo clocks is shown in
istics” on page
input clock (K) of the DDR-II+. The timing for the echo clocks is shown in
istics” on page
0
controls D
[35:27]
22.
22.
.
[3:0]
[7:0]
[8:0]
[17:0]
[35:0]
and NWS
0
0
0
controls D
controls D
controls D
[x:0]
1
controls D
are automatically tri-stated.
[8:0]
[8:0]
[8:0]
, BWS
[x:0]
[x:0]
and BWS
Pin Description
when in single clock mode. All accesses are initiated
[7:4]
when in single clock mode.
1
controls D
.
1
controls D
CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18
[17:9]
, BWS
[17:9].
2
controls D
“Switching Character-
“Switching Character-
[26:18]
and BWS
Page 6 of 27
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