LH28F160S5T-L70A Sharp Microelectronics, LH28F160S5T-L70A Datasheet - Page 6

• Manufacturer Part Number: LH28F160S5T-L70A
• Description: IC FLASH 16MBIT 70NS 56TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F160S5T-L70A

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (2M x 8 or 1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 56-TSOP
• Other names: 425-1840; LHF16KA9

sharp
1 INTRODUCTION
This
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.
1.1 Product Overview
The LH28F160S5T-L70A is a high-performance 16M-
bit
2MBx8/1MBx16. The 2MB of data is arranged in
thirty-two 64K-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.
Smart 5 technology provides a choice of V
V
system performance and power expectations. 5V V
provides the highest read performance. V
eliminates the need for a separate 12V converter,
while
performance. In addition to flexible erase and
program voltages, the dedicated V
complete data protection when V
Internal
automatically configures the device for optimized
read and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
A block erase operation erases one of the device’s
64K-byte blocks typically within 0.34s (5V V
V
independently erased 100,000 times (3.2 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
A word/byte write is performed in byte increments
typically within 9.24µs (5V V
word/byte write has high speed write performance of
2µs/byte (5V V
suspend mode enables the system to read data or
PP
PP
Table 1. V
) independent of other blocks. Each block can be
Smart
combinations, as shown in Table 1, to meet
V
datasheet
V
CC
PP
Offered by Smart 5 Technology
V
Voltage
5V
=5V
CC
CC
5
CC
and V
and
, 5V V
Flash
maximizes
contains
PP
PP
V
Voltage Combinations
PP
memory
). (Multi) Word/byte write
CC
LH28F160S5T-L70A
PP
detection
erase
, 5V V
V
≤V
PP
PPLK
organized
Voltage
5V
PP
PP
and
.
). A multi
pin gives
PP
Circuitry
CC
CC
at 5V
write
, 5V
and
LHF16KA9
CC
as
execute code from any other flash memory array
location.
Individual block locking uses a combination of bits
and WP#, Thirty-two block lock-bits, to lock and
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus
(interrupt masking for background block erase, for
example). Status polling using STS minimizes both
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults to
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration.
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi)
word/byte write are inactive, (multi) word/byte write
are suspended, or the device is in deep power-down
mode. The other 3 alternate configurations are all
pulse mode for use as a system interrupt.
The access time is 70ns (t
temperature range (0°C to +70°C) and V
voltage range of 4.75V-5.25V. At lower V
the access time is 80ns (4.5V-5.5V).
The
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical I
When either CE
the I
RP# pin is at GND, deep power-down mode is
enabled which minimizes power consumption and
provides write protection during reset. A reset time
(t
outputs are valid. Likewise, the device has a wake
time (t
recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 56-Lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in
Figure 2.
PHQV
CC
Automatic
) is required from RP# switching high until
PHEL
CMOS standby mode is enabled. When the
software
) from RP#-high until writes to the CUI are
0
# or CE
CCR
Power
polling)
current is 1 mA at 5V V
1
#, and RP# pins are at V
AVQV
Savings
and
) over the commercial
status
(APS)
CC
CC
Rev. 2.0
masking
voltage,
CC
feature
supply
.
CC
3
,