LH28F008SCT-L85 Sharp Microelectronics, LH28F008SCT-L85 Datasheet
LH28F008SCT-L85
Specifications of LH28F008SCT-L85
F008SCTL85
LHF08CH1
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LH28F008SCT-L85 Summary of contents
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... P S RODUCT PECIFICATIONS LH28F008SCT-L85 Flash Memory (Model No.: LHF08CH1) Issue Date: April 24, 2000 ® 8M (1MB × 8) Spec No.: EL104027C Integrated Circuits Group ...
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Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ●When using the products covered herein, please ...
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INTRODUCTION ................................................... 3 1.1 New Features...................................................... 3 1.2 Product Overview ................................................ 3 2.0 PRINCIPLES OF OPERATION ............................. 7 2.1 Data Protection ................................................... 7 3.0 BUS OPERATION................................................. 8 3.1 Read ................................................................... 8 3.2 Output Disable .................................................... 8 3.3 Standby ...
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... Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F008SCT-L85 offers three levels of protection: absolute protection with V GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28F008SCT-L85 is manufactured on SHARP’ ...
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... SmartVoltage technology, allow V connection to 3.3V or 5V. PP 1.2 Product Overview The LH28F008SCT-L85 is a high-performance 8M-bit SmartVoltage Flash memory organized as 1M-byte of 8 bits. The 1M-byte of data is arranged in sixteen 64K-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Figure 3 ...
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Individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. configuration operations ...
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Input Buffer Address Latch Address Counter CE ...
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... INPUT 0 19 are internally latched during a write cycle. DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs INPUT/ data during memory array, status register, and identifier code read cycles. Data pins float DQ - OUTPUT to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE: Activates the device’ ...
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... PRINCIPLES OF OPERATION The LH28F008SCT-L85 SmartVoltage Flash memory includes an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with RAM-Like interface timings ...
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... BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, or status register independent of the V voltage. RP# can be at either V ...
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... Lock) or block within the device (Block Lock locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first) ...
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... Table 3. Bus Operations RP# CE# OE# WE ≤V , memory contents can be read, but not altered. PP PPLK or V PPLK during a write operation Address V DQ RY/BY OUT X X High High High Z See X Note 5 Figure for V . See DC Characteristics for PPH1/2 PPH1/2/3 <3. <RP#<V produce Rev. 1 ...
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... IA=Identifier Code Address: see Figure 4. BA=Address within the block being erased or locked. WA=Address of memory location to be written. 3. SRD=Data read from status register. See Table 7 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first) ...
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... Future Use NOTE selects the specific block lock configuration code to be read. See Figure 4 for the device identifier code memory map. LHF08CH1 4.3 Read Status Register Command The status register may be read to determine when a block erase, byte write, or lock-bit configuration is complete and whether the operation completed successfully ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and ...
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... The only other valid commands while byte write is suspended are Read Status Register and Byte Write Resume. After Byte Write Resume command is written to the flash memory, the WSM will continue the byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to V ...
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Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the ...
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WSMS ESS 7 6 SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITS STATUS ...
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Start Write 20H, Block Address Write D0H, Block Address Read Status Register No 0 Suspend SR.7= Block Erase 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V ...
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Start Write 40H, Address Write Byte Data and Address Read Status Register No 0 Suspend SR.7= Byte Write 1 Full Status Check if Desired Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above SR.3= ...
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Start Write B0H Read Status Register 0 SR. SR.6= 1 Read or Read Byte Write ? Read Array Data Byte Write Loop No Done? Yes Write D0H Block Erase Resumed LHF08CH1 Bus Operation Write Read Standby Standby ...
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Start Write B0H Read Status Register 0 SR. SR.2= Byte Write Completed 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Read Array Data Byte Write Resumed LHF08CH1 Bus Operation Write Read ...
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Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above SR. Device ...
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Start Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above SR. Device Protect Error SR.1= ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three accommodate multiple memory Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’ ...
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... After block erase, byte write, or lock-bit configuration, even after V transitions down must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block erasure, byte writing, or lock-bit ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Byte Write and Lock-Bit Configuration ...........0°C to +70°C Temperature under Bias............... -10°C to +80°C Storage Temperature........................ -65°C to +125°C Voltage On Any Pin (except V , ...
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AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times ...
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DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down CCD CC Current I V Read Current CCR Byte Write or ...
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Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout during PPLK PP Normal Operations V V ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS Sym. t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# ...
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Versions Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# to Output in ...
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Standby V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - RP#(P) V ...
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AC CHARACTERISTICS - WRITE OPERATION Sym. t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t Address Setup to WE# ...
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Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t RP# V Setup to WE# Going High ...
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ADDRESSES(A) CE#(E) OE#(G) WE#(W) DATA(D/Q) RY/BY#(R) RP#(P) V (V) PP NOTES power-up and standby Write block erase or byte write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or ...
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ALTERNATIVE CE#-CONTROLLED WRITES Sym. t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t Address Setup to CE# Going High ...
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Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t RP# V Setup to CE# Going High ...
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ADDRESSES(A) WE#(W) OE#(G) CE#(E) DATA(D/Q) RY/BY#(R) RP#(P) V (V) PP NOTES power-up and standby Write block erase or byte write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or ...
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RESET OPERATIONS V OH RY/BY#( RP#( RY/BY#( RP#( 2.7V/3.3V/ RP#( Sym. Parameter RP# Pulse Low Time ...
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BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE Sym. Parameter t WHQV1 Byte Write Time t EHQV1 Block Write Time t WHQV2 Block Erase Time t EHQV2 t WHQV3 Set Lock-Bit Time t EHQV3 t WHQV4 Clear Block ...
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... Device Density 008 = 8-Mbit Architecture S = Regular Block Power Supply Type C = SmartVoltage Technology Operating Temperature Blank = 0°C ~ +70° -40°C ~ +85°C Option Order Code 1 LH28F008SCT-L85 LH28F008SC-L150 LH28F008SC-L120 LH28F008SC-L90 LHF08CH1 - Package T = 40-Lead TSOP R = 40-Lead TSOP(Reverse Bend 44-Lead PSOP 48-Ball CSP Valid Operational Combinations V =2.7-3.6V V =3.3± ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED event will SHARP be liable any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 ...