AT49LH00B4-33JC SL383 Atmel, AT49LH00B4-33JC SL383 Datasheet - Page 9

• Manufacturer Part Number: AT49LH00B4-33JC SL383
• Description: IC FLASH 4MBIT 33MHZ 32PLCC
• Manufacturer: Atmel

Specifications of AT49LH00B4-33JC SL383

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
3379C–FLASH–3/05
Start Field
IDSEL (Device Select) Field
MADDR (Memory Address) Field
Msize (Memory Size) Field
Additional Fields for FWH Memory Cycles
TAR (Turn-around) Field
Figure 7-1.
This 1-clock field indicates the start of a cycle. It is valid on the last clock that FWH4/LFRAME is
sampled low. The two start fields that are used for a FWH cycle are: 1101b to indicate a FWH
memory read cycle and 1110b to indicate a FWH memory write cycle. If the start field that is
sampled is not one of these values, then the cycle attempted is not a FWH memory cycle. It may
be a valid LPC memory cycle that the device will attempt to decode.
This 1-clock field is used to indicate which FWH component in the system is being selected. The
four bits transmitted over FWH/LAD[3:0] during this clock are compared with values strapped on
the ID[3:0] pins. If there is a match, the device will continue to decode the cycle to determine
which bytes are requested on a read or which bytes to update on a write. If there isn’t a match,
the device may discard the rest of the cycle and go into a standby power state.
This is a 7-clock field that is used to provide a 28-bit (A27 - A0) memory address. This allows for
provisioning of up to 256 MB per FWH memory device, for a total of a 4 GB addressable space if
16 FWH memory devices (256 MB each) were used in a system.
The AT49LH00B4 only decodes the last six MADDR nibbles (A23 - A0) and ignores address bits
A27 - A23 and A21 - A19. Address bit A22 is used to determine whether reads or writes to the
device will be directed to the memory array (A22 = 1) or to the register space (A22 = 0).
Addresses are transferred to the device with the most significant nibble first.
The 1-clock MSIZE is used to indicate how many bytes of data will be transferred during a read
or write. The AT49LH00B4 only supports single-byte transfers, so 0000b must be sent in this
field to indicate a single-byte transfer.
Additional fields are required to complete a FWH read or write cycle. The placement of these
fields, in addition to the data field, depends on whether the cycle is a FWH read or write. The
FWH Read Cycle and FWH Write Cycle sections detail the order of the various fields.
This 2-clock field is driven by the master when it is turning control over to the FWH memory
device, and it is driven by the FWH device when it is turning control back over to the master. On
the first clock of the TAR field, the master or FWH drives the FWH/LAD[3:0] lines to 1111b. On
the second clock, the master or FWH device puts the FWH/LAD[3:0] lines into a high-impedance
state.
FWH4/LFRAME
FWH/LAD[3:0]
CLK
FWH Memory Cycle Initiation and Addressing
START
IDSEL
MADDR MADDR MADDR
MADDR
MADDR MADDR MADDR
AT49LH00B4
MSIZE
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