M48Z18-100PC1 STMicroelectronics, M48Z18-100PC1 Datasheet - Page 8

• Manufacturer Part Number: M48Z18-100PC1
• Description: IC NVSRAM 64KBIT 100NS 28DIP
• Manufacturer: STMicroelectronics

Specifications of M48Z18-100PC1

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 64K (8K x 8)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP Module (600 mil), 28-EDIP
• Data Bus Width: 8 bit
• Organization: 8 Kb x 8
• Interface Type: Parallel
• Access Time: 100 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Operating Current: 80 mA
• Maximum Operating Temperature: 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Capacitance, Input: 10 pF
• Capacitance, Output: 10 pF
• Current, Input, Leakage: ±1 μA
• Current, Operating: 80 mA
• Current, Output, Leakage: ±1
• Data Retention: 11 yrs.
• Density: 64K
• Package Type: PCDIP28
• Power Dissipation: 1 W
• Temperature, Operating: 0 to +70 °C
• Time, Access: 100 ns
• Time, Fall: ≤5 ns
• Time, Rise: ≤5 ns
• Voltage, Input, High: 4.8 to 5.8 V
• Voltage, Input, Low: 0.8 V
• Voltage, Output, High: 2.4 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 4.5 to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2877-5

Operation modes
Figure 4.
Note:
Table 3.
1. Valid for ambient operating temperature: T
2. C
2.2
8/20
Symbol
t
t
t
t
GHQZ
ELQX
GLQX
EHQZ
t
t
t
t
L
t
AVQV
GLQV
AXQX
ELQV
AVAV
= 30 pF.
(2)
(2)
(2)
(2)
A0-A12
E
G
DQ0-DQ7
READ mode AC waveforms
WRITE enable (W) = high.
READ mode AC characteristics
WRITE mode
The M48Z08/18 is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W or E.
A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held
valid throughout the cycle. E or W must return high for a minimum of t
or t
in must be valid t
should be kept high during WRITE cycles to avoid bus contention; although, if the output bus
has been activated by a low on E and G, a low on W will disable the outputs t
falls.
READ cycle time
Address valid to output valid
Chip enable low to output valid
Output enable low to output valid
Chip enable low to output transition
Output enable low to output transition
Chip enable high to output Hi-Z
Output enable high to output Hi-Z
Address transition to output transition
WHAX
from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-
Parameter
DVWH
prior to the end of WRITE and remain valid for t
tAVQV
A
tELQX
= 0 to 70 °C; V
tGLQX
tELQV
(1)
tGLQV
Doc ID 2424 Rev 7
tAVAV
VALID
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
Min
100
10
5
5
M48Z08/M48Z18
VALID
tGHQZ
Max
100
100
50
50
40
EHAX
WHDX
M48Z08, M48Z18
from chip enable
tAXQX
tEHQZ
afterward. G
WLQZ
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
AI01385
after W