MAX195EVKIT-DIP Maxim Integrated, MAX195EVKIT-DIP Datasheet - Page 7

• Manufacturer Part Number: MAX195EVKIT-DIP
• Description: Data Conversion IC Development Tools Programmers, Development Systems
• Manufacturer: Maxim Integrated
• Series: MAX195r

Specifications of MAX195EVKIT-DIP

• Interface Type: QSPI, Serial (SPI, Microwire)
• Factory Pack Quantity: 1

The analog input to the MAX194 may be buffered by
U8. A MAX400 is used because of its low V
feedback circuit consists of four passive components:
R41, R61, C171, and R51. R41 isolates the op-amp’s
output from the dynamic capacitive load at the AIN
input. R61 makes the network accurate at the reference
input (without R61, the reference voltage would appear
at the output of the op amp). C171 compensates the
high-frequency response by making R51 dominate at
high frequencies.
Input offset may be improved by adding a 1000pF to
0.01µF ceramic capacitor at site C28.
The voltage reference U2 provides a 4.096V reference,
which is buffered by U5. The buffer isolates the refer-
ence from the MAX194’s capacitive switching load. To
eliminate the buffer circuit, cut traces JU8 and JU9 and
connect a wire from JU9 pin 1 to the VREF pad.
The reference input to the MAX194 may be buffered by
U5. The MAX400 op amp is used because of its low
V
amp, the substrate can be connected to the quiet ana-
log ground, reducing the noise coupled through the
power supplies. The feedback circuit consists of four
passive components: R4, R6, C17, and R5. R4 isolates
the op-amp’s output from the heavy capacitive load
that bypasses the VREF pin. R6 makes the network
accurate at the reference input (without R6, the refer-
ence voltage would appear at the output of the op
Table 7. Data-Interface Connections
OS
drift. By using a bipolar (instead of CMOS) op
28, 29, 30
PIN NO.
33, 34
39, 40
9–26
1–4
5, 6
7, 8
27
31
32
35
36
37
38
MAX194 Evaluation System/Evaluation Kit
_______________________________________________________________________________________
68HC16 SIGNAL
Reserved
Reserved
Reserved
Reserved
Reserved
MISO
PCS0
+12V
GND
OC2
OC3
SCK
+5V
IC1
Analog Input Buffer
Voltage Reference
Reference Buffer
MAX194 SIGNAL
BP/UP/SHDN
OS
Reserved
Reserved
Reserved
Reserved
Reserved
RESET
VDDD
DOUT
+12V
GND
EOC
CLK
drift. The
CS
Ground
Unregulated 12V DC Supply
Regulated +5V DC from 68HC16 Module
Reserved
End-of-Conversion Output from MAX194
Reserved
Active-Low RESET to MAX194
Shutdown/Bipolar/Unipolar Input to MAX194
Reserved
QSPI Master Input; Serial Data Output from MAX194
Reserved
QSPI Serial Clock from 68HC16
QSPI Chip-Select from 68HC16
Reserved
amp). C17 compensates the high-frequency response
by making R5 dominate at high frequencies.
The reference buffer U5 draws its power through the
lowpass filter formed by R3 and C18. The filter provides
the necessary power-supply rejection. U5 is powered
by the unregulated input supply to ensure enough
headroom to buffer the 4.096V reference.
Good PC board layout necessary to achieve specified
performance, and an analog ground plane is essential
for optimum performance. The PC board layout artist
must be provided with explicit instructions, preferably a
pencil sketch of the placement of sensitive analog com-
ponents and the routing of ground connections. See
the EV kit PC board layout for an example. Use the fol-
lowing guidelines:
1) At the schematic level, keep the analog power sup-
2) Cluster the MAX194, the voltage reference, and any
3) Keep the analog-input signal ground return sepa-
plies and grounds separate from all other power
supplies and grounds. Digital power may be con-
nected to analog power through a 10Ω series resis-
tor to attenuate digital noise.
input or reference buffers near the site where the
analog signal enters the board. Place 0.1µF ceramic
decoupling capacitors within 10mm of the MAX194’s
power-supply and voltage-reference pins.
rate from the analog ground plane, connecting to
analog ground only at the AGND pin of the
MAX194. The analog input and its signal ground-
return traces should both follow the same route to
help reject common-mode noise.
Layout, Power Supplies, and Grounding
FUNCTION
7