MAX195EVKIT-DIP Maxim Integrated, MAX195EVKIT-DIP Datasheet - Page 16

• Manufacturer Part Number: MAX195EVKIT-DIP
• Description: Data Conversion IC Development Tools Programmers, Development Systems
• Manufacturer: Maxim Integrated
• Series: MAX195r

Specifications of MAX195EVKIT-DIP

• Interface Type: QSPI, Serial (SPI, Microwire)
• Factory Pack Quantity: 1

The 68HC16 uses a phase-locked loop (PLL) to set its
bus speed. Crystal Y1 is a 32.768kHz frequency refer-
ence. The internal oscillator runs 256 times faster than
the external crystal. When the 68HC16 is reset, it waits
for the PLL to lock before it executes any software. After
the PLL locks onto the reference frequency, the soft-
ware doubles the clock speed by writing to the clock
synthesizer control register, selecting a bus speed of
16.78MHz.
U5, the user RAM area, is a 32kbyte CMOS static RAM.
The 74HCT245 octal buffer lets the 68HC16 module
access an 8-bit port on the 40-pin interface connector.
This memory-mapped port consists of separate read
and write strobes, four chip selects, four address LSBs,
and eight data bits.
J3 is an RS-232 serial port, designed to be compatible
with the IBM PC 9-pin serial port. Use a straight-through
DB9 male-to-female cable to connect J3 to this port. If
the only available serial port has a 25-pin connector,
you may use a standard 25-pin to 9-pin adapter. Table
9 shows the pinout of J3.
The MAX233 is an RS-232 interface voltage level shifter
with two transmitters and two receivers. It includes a
built-in charge pump with internal capacitors that gen-
erates the output voltages necessary to drive RS-232
lines.
The 20 x 2 pin header connects the 68HC16 module to
a Maxim EV kit. Table 10 lists the function of each pin.
Note that 68HC16 object code is not compatible with
68HC11 object code. Use the 68HC16 module only
with those modules that are designed to support it, and
only download code that is targeted for the 68HC16
module. Downloading incorrect object code into the
68HC16 module will have unpredictable results.
The 68HC16 µC generates various enable signals for
different address ranges. The ROM and RAM enable
signals are fed directly to the respective chips. Several
additional signals (J1.11–J1.14) are available on the
data connector to be used by Maxim EV kits. Table 11
outlines the address ranges for each of the elements
found on the 68HC16 module, and Table 12 is a truth
table that describes the logic for each of the 68HC16’s
chip-select outputs. Because the addresses are not
completely decoded, the boot ROM and user RAM
have shadows.
MAX194 Evaluation System/Evaluation Kit
16
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40-Pin Data Connector J1
Serial Communications
Address Ranges
Table 9. Serial Communications Port J3
Table 10. 40-Pin Data-Connector Signals
PIN
20–26
1
2
3
4
5
6
7
8
9
PIN
1–4
5, 6
7, 8
10
11
12
13
14
15
16
17
18
19
27
28
29
30
31
32
33
34
35
36
37
38
39
40
9
NAME
None
DCD
GND
RXD
DSR
TXD
DTR
RTS
CTS
VPREREG
EXTD1–7
PCS0/SS
CLKOUT
EXTD0
NAME
PWMA
7E000
7E800
7F000
7F800
MISO
MOSI
GND
VCC
OC1
OC2
OC3
OC4
SCK
A00
A01
A02
A03
WR
IC1
IC2
IC3
IC4
RD
Handshake; hard-wired to DTR and DSR
RS-232-compatible data output from
68HC16 module
RS-232-compatible data input to
68HC16 module
Handshake; hard-wired to DCD and DSR
Signal ground connection
Handshake; hard-wired to DCD and DTR
Handshake; hard-wired to CTS
Handshake; hard-wired to RTS
Unused
Ground
Unregulated input voltage
+5V from on-board regulator
Read strobe
Write strobe
Chip select for 7E000–7E7FF
Chip select for 7E800–7EFFF
Chip select for 7F000–7F7FF
Chip select for 7F800–7FFFF
Address bit 0 (LSB)
Address bit 1
Address bit 2
Address bit 3
Buffered data bus 0 (LSB)
Buffered data bus bits 1–7
General I/O port bit 0 (LSB)
General I/O port bit 1
General I/O port bit 2
General I/O port bit 3
General I/O port bit 4
General I/O port bit 5
General I/O port bit 6
General I/O port bit 7
QSPI master-in, slave-out
QSPI master-out, slave-in
QSPI serial clock
QSPI chip-select output
System clock output
Pulse-width-modulator output
FUNCTION
FUNCTION