CY7C1320BV18-250BZC Cypress Semiconductor Corp, CY7C1320BV18-250BZC Datasheet

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... CY7C1318BV18) of two 36-bit words (in the case of CY7C1320BV18) sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same ...

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... Logic Block Diagram (CY7C1916BV18 (19:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [0] Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Write Write Reg Reg Output Logic Control Read Data Reg Reg. Reg. 8 Reg. Write Write Reg Reg Output Logic Control Read Data Reg ...

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... Logic Block Diagram (CY7C1318BV18) Burst A0 Logic (19:0) A Address (19:1) Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [1:0] Logic Block Diagram (CY7C1320BV18) Burst A0 Logic (18:0) A Address (18:1) Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [3:0] Document Number: 38-05621 Rev. *D ...

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... Pin Configuration The pin configuration for CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follow NC/72M DQ4 DQ5 H DOFF V V REF DDQ DQ6 DQ7 R TDO TCK NC/72M DQ4 DQ5 H DOFF V V REF DDQ DQ6 DQ7 R TDO TCK A Note 1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level. ...

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... Pin Configuration (continued) The pin configuration for CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follow NC/72M DQ9 DQ10 DQ11 F NC DQ12 DQ13 H DOFF V V REF DDQ DQ14 L NC DQ15 DQ16 DQ17 R TDO TCK NC/144M NC/36M B NC DQ27 DQ18 DQ28 D NC DQ29 DQ19 E NC ...

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... CY7C1318BV18 – the input to the burst counter. These are incremented internally in a linear fashion. 20 address inputs are needed to access the entire memory array. CY7C1320BV18 – the input to the burst counter. These are incremented internally in a linear fashion. 19 address inputs are needed to access the entire memory array. All the address inputs are ignored when the appropriate port is deselected ...

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... Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Pin Description Switching Characteristics on page 23. Switching Characteristics on page 23. output impedance are set to 0.2 x RQ, where resistor connected [x:0] ...

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... Functional Overview The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface. Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of the output clocks (C/C, or K/K when in single clock mode) ...

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... Vterm = 0.75V Source CLK# Echo Clock1/Echo Clock#1 Echo Clock2/Echo Clock#2 Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in Characteristics on page 23. DLL These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock = 1 ...

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... Device powers up deselected with the outputs in a tri-state condition CY7C1318BV18 and CY7C1320BV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses sequence in the burst. On CY7C1316BV18 and CY7C1916BV18, “A1” represents A + ‘0’ and “A2” represents A + ‘1’. ...

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... L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into the device during this portion of a write operation. Write Cycle Descriptions The write cycle description table for CY7C1320BV18 follows. BWS BWS BWS BWS ...

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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 15 ...

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... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...

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... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 [9] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- ...

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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 11. Overshoot: V (AC) < 0.85V (Pulse width less than t IH DDQ 12. All Voltage referenced to Ground. Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 0 Bypass Register Instruction Register ...

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... CS CH 14. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Description [14] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50Ω ...

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... Do not use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Value CY7C1916BV18 CY7C1318BV18 000 000 00000110100 00000110100 ...

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... Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Bump ID Bit # Bump ID 11H 54 7B 10G 11F 57 5B 11G 10F 60 5C 11E 61 4B 10E 62 3A 10D 10C 65 2B 11D 66 3B ...

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... DDQ DOFF Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 DLL Constraints ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as t ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior ...

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... V REF DDQ 19. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Latch up Current..................................................... >200 mA Operating Range Range Commercial ...

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... I Automatic Power Down SB1 Current AC Electrical Characteristics [11] Over the Operating Range Parameter Description V Input HIGH Voltage IH V Input LOW Voltage IL Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Test Conditions V = Max, 200 MHz (x8 mA, (x9) OUT 1/t MAX CYC (x18) (x36) 167 MHz ...

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... RQ = 250Ω (a) Note 20. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V levels of 0.25V to 1.25V, and output loading of the specified I Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Test Conditions T = 25° MHz 1.8V DDQ Test Conditions ...

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... This part has an internal voltage regulator; t POWER 23. For DQ2 data signal on CY7C1916BV18 device, t Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 300 MHz 278 MHz Min Max Min Max Min Max Min Max Min Max [22] 1 – ...

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... CHZ CLZ 25. At any voltage and temperature t is less than t CHZ Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 300 MHz 278 MHz Min Max Min Max Min Max Min Max Min Max – 0.45 – 0.45 – ...

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... Outputs are disabled (High-Z) one clock cycle after a NOP. 28. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 [26, 27, 28] NOP NOP ...

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... CY7C1316BV18-278BZXI CY7C1916BV18-278BZXI CY7C1318BV18-278BZXI CY7C1320BV18-278BZXI Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( ...

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... Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code 250 CY7C1316BV18-250BZC CY7C1916BV18-250BZC CY7C1318BV18-250BZC CY7C1320BV18-250BZC CY7C1316BV18-250BZXC CY7C1916BV18-250BZXC CY7C1318BV18-250BZXC CY7C1320BV18-250BZXC CY7C1316BV18-250BZI CY7C1916BV18-250BZI CY7C1318BV18-250BZI CY7C1320BV18-250BZI CY7C1316BV18-250BZXI CY7C1916BV18-250BZXI ...

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... CY7C1316BV18-167BZXI CY7C1916BV18-167BZXI CY7C1318BV18-167BZXI CY7C1320BV18-167BZXI Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( ...

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... Package Diagram Figure 6. 165-Ball FBGA ( 1.4 mm), 51-85180 TOP VIEW PIN 1 CORNER 13.00±0.10 SEATING PLANE C Document Number: 38-05621 Rev. *D CY7C1316BV18, CY7C1916BV18 CY7C1318BV18, CY7C1320BV18 0.15(4X) BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. -0.06 Ø0.50 (165X) +0. 1.00 5.00 10.00 13.00±0.10 NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0 ...

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... Document History Page Document Title: CY7C1316BV18/CY7C1916BV18/CY7C1318BV18/CY7C1320BV18, 18-Mbit DDR-II SRAM 2-Word Burst Ar- chitecture Document Number: 38-05621 Submission Orig, of Rev. ECN No. Date Change ** 252474 See ECN SYT *A 325581 See ECN SYT *B 413997 See ECN NXR *C 472384 See ECN NXR Document Number: 38-05621 Rev. *D ...

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... Document History Page Document Title: CY7C1316BV18/CY7C1916BV18/CY7C1318BV18/CY7C1320BV18, 18-Mbit DDR-II SRAM 2-Word Burst Ar- chitecture Document Number: 38-05621 *D 2511674 06/03/08 VKN/PYRS Updated Logic Block diagrams Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...