W9425G6JH-5 Winbond Electronics, W9425G6JH-5 Datasheet - Page 9
W9425G6JH-5
Manufacturer Part Number
W9425G6JH-5
Description
IC DDR-400 SDRAM 256MB 66TSSOPII
Manufacturer
Winbond Electronics
Datasheet
1.W9425G6JH-5.pdf
(52 pages)
Specifications of W9425G6JH-5
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
256M (16Mx16)
Speed
250MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOPII
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
W9425G6JH-5
Manufacturer:
INFINEON
Quantity:
763
Company:
Part Number:
W9425G6JH-5
Manufacturer:
WINBOND
Quantity:
5 800
Company:
Part Number:
W9425G6JH-5
Manufacturer:
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Quantity:
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Company:
Part Number:
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Manufacturer:
WINBOND
Quantity:
2 890
Company:
Part Number:
W9425G6JH-5
Manufacturer:
WINBOND
Quantity:
5
Part Number:
W9425G6JH-5
Manufacturer:
WINBOND/华邦
Quantity:
20 000
7. FUNCTIONAL DESCRIPTION
7.1
Command
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
CLK
CLK
Power Up Sequence
1) Apply V
2) Apply V
Apply power and attempt to CKE at a low state ( ≤ 0.2V), all other inputs may be undefined
Start Clock and maintain stable condition for 200 µS (min.).
After stable power and clock, apply NOP and take CKE high.
Issue precharge command for all banks of the device.
Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type.
Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8.
(An additional 200 cycles(min) of clock are required for DLL Lock before any executable
command applied.)
Issue precharge command for all banks of the device.
Issue two or more Auto Refresh commands.
Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low.
maintain stable
for 200 µS min.
PREA
Inputs
t
DD
DDQ
RP
before or at the same time as V
Enable DLL
before or at the same time as V
EMRS
2 Clock min.
Initialization sequence after power-up
DLL reset with A8 = High
MRS
2 Clock min.
PREA
- 9 -
t
RP
DDQ
TT
AREF
.
and V
200 Clock min.
REF
t
Publication Release Date: May 26, 2010
RFC
.
AREF
W9425G6JH
t
RFC
Disable DLL reset with A8 = Low
Revision A01
MRS
2 Clock min.
CMD
ANY