C8051F509-IMR Silicon Labs, C8051F509-IMR Datasheet - Page 167

• Manufacturer Part Number: C8051F509-IMR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 64 kB 4 kB SPI UART I2C
• Manufacturer: Silicon Labs

Specifications of C8051F509-IMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

19.2. Programmable Internal Oscillator
All C8051F50x/F51x devices include a programmable internal high-frequency oscillator that defaults as the
system clock after a system reset. The internal oscillator period can be adjusted via the OSCICRS and
OSCIFIN registers defined in SFR Definition 19.3 and SFR Definition 19.4. On C8051F50x/F51x devices,
OSCICRS and OSCIFIN are factory calibrated to obtain a 24 MHz base frequency. Note that the system
clock may be derived from the programmed internal oscillator divided by 1, 2, 4, 8, 16, 32, 64, or 128, as
defined by the IFCN bits in register OSCICN. The divide value defaults to 128 following a reset.
19.2.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
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When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals
resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes
execution at the instruction following the write to SUSPEND.
Note: When entering suspend mode, firmware must set the ZTCEN bit in REF0CN (SFR Definition 8.1).
Port 0 Match Event.
Port 1 Match Event.
Port 2 Match Event.
Port 3 Match Event.
Comparator 0 enabled and output is logic 0.
Rev. 1.2
C8051F50x/F51x
167